Reduced number of masks for IC device with stacked contact levels
First Claim
1. A method, for use with a three-dimensional stacked IC device having a stack of contact levels at an interconnect region, for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, the method comprising:
- using a set of N etch masks for creating up to and including 2N levels of interconnect contact regions at the stack of the contact levels, each mask comprising mask and etch regions, N being an integer equal to at least 2, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N;
removing at least a portion of any upper layer overlying the stack of the contact levels at the interconnect region;
etching the interconnect region N times using said masks in a chosen order to create contact openings extending from a surface layer to each contact level, the contact openings being aligned with and providing access to the landing areas at each of the 2N contact levels; and
the etching step comprising etching through 2x−
1 contact levels for each mask of sequence number x;
whereby electrical conductors can be formed through the contact openings to contact the landing areas at the contact levels.
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Accused Products
Abstract
A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x−1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
34 Citations
17 Claims
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1. A method, for use with a three-dimensional stacked IC device having a stack of contact levels at an interconnect region, for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, the method comprising:
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using a set of N etch masks for creating up to and including 2N levels of interconnect contact regions at the stack of the contact levels, each mask comprising mask and etch regions, N being an integer equal to at least 2, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N; removing at least a portion of any upper layer overlying the stack of the contact levels at the interconnect region; etching the interconnect region N times using said masks in a chosen order to create contact openings extending from a surface layer to each contact level, the contact openings being aligned with and providing access to the landing areas at each of the 2N contact levels; and the etching step comprising etching through 2x−
1 contact levels for each mask of sequence number x;whereby electrical conductors can be formed through the contact openings to contact the landing areas at the contact levels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for providing electrical connections to landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device of a type comprising an interconnect region, the interconnect region including an upper layer with a stack of at least first, second, third and fourth contact levels beneath the upper layer, the method comprising:
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forming at least first and second openings in the upper layer, each opening exposing a surface portion of a first contact level, the first and second openings partially bounded by upper layer sidewalls; depositing a sidewall material on the sidewalls of each of the first and second openings and on a first part of each of the surface portions while leaving a second part of the surface portions without sidewall material thereon; extending the first and second openings through the second parts of the surface portions to expose a surface of the second contact level for each of the first and second openings; removing at least some of the sidewall material at each opening to expose at least some of the first part of the surface portion at each opening, thereby forming interconnect contact regions at the second openings, the interconnect contact regions at the second opening aligned with the landing areas at the first and second contact levels; further extending the first opening from (1) the exposed first part of the surface portion, through the first and second contact levels to expose a surface of a third contact level, and (2) an exposed surface of the second contact level through the second and third contact levels to expose a surface of the fourth contact level, thereby forming the interconnect contact regions at the first opening aligned with the landing areas at the third and fourth contact levels; and forming electrical conductors to the landing areas at the first, second, third and fourth contact levels. - View Dependent Claims (16, 17)
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Specification