MOSFET with integrated field effect rectifier

• US 8,598,620 B2
• Filed: 04/28/2009
• Issued: 12/03/2013
• Est. Priority Date: 09/26/2007
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics NV
• Inventors: Ankoudinov, Alexei, Rodov, Vladimir, Cordell, Richard
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US12/431,580
• Publication Number:
  US 20090267111A1
• Time in Patent Office: 1,680 Days
• Field of Search: 257/130, 257/107, 257/E29.169, 257124-127, 257/133, 257/155, 257/159, 257/118, 257/135, 257/142, 257/137, 257/143, 257/153, 257/119, 257/138
• US Class Current: 257/124
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 μm technology. Self-aligned processing can be used.

Claims

1. An apparatus comprising:

a metal oxide semiconductor field effect transistor (MOSFET) having a first gate, a source, a drain, and a first gate oxide, wherein the current flow between the source and the drain is controlled by the voltage applied to the first gate; and

a field effect rectifier connected between the source and the drain and serving to shunt current therethrough during switching of the MOSFET, the field effect rectifier comprising a second gate and a second gate oxide,

wherein a first gate oxide of the MOSFET and the second gate oxide of the field effect rectifier have different thicknesses.

2. The apparatus of claim 1 wherein the MOSFET is a DMOS structure.

3. The apparatus of claim 1 where the MOSFET is a UMOS structure.

4. The apparatus of claim 1 formed using a self-aligned process.

5. The apparatus of claim 1 formed using not greater than 0.25 μ

m processing.

6. The apparatus of claim 1 formed using N-epitaxial processing.

7. The apparatus of claim 1 formed using multi-epitaxial processing.

8. The apparatus of claim 1 formed using supertrench processing.

9. A semiconductor structure comprising:

a DMOS-type transistor;

a field effect rectifier formed in the same substrate as said transistor and connected to shunt shunt current away from a body diode of the DMOS-type transistor, the field effect rectifier comprising a second gate, a second gate oxide, a drift region, and a p-type adjustment region within said drift region,

wherein the first gate oxide of the DMOS-type transistor and the second gate oxide of the field effect rectifier have different thicknesses.

10. The structure of claim 9, wherein said source is n-type, and is surrounded by a p-type body region.

11. The structure of claim 9, wherein said field effect rectifier has a respective gate electrode which is formed from the same thin film layer as said gate of said transistor.

12. The structure of claim 9, wherein said transistor and said field effect rectifier both comprise MOS gate structures, but have different respective gate dielectric thicknesses.

13. The structure of claim 9, wherein said drain is n-type.