Semiconductor device and driving method of semiconductor device

• US 8,598,648 B2
• Filed: 03/10/2011
• Issued: 12/03/2013
• Est. Priority Date: 03/19/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Okamoto, Satohiro, Nagatsuka, Shuhei
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US13/044,674
• Publication Number:
  US 20110227062A1
• Time in Patent Office: 999 Days
• Field of Search: 257/316, 257/326, 257/390, 365/189.19
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

m (m is an integer greater than or equal to

     2) signal lines;

m word lines;

a selection line;

first to m-th memory cells connected in series between the source line and the bit line; and

a selection transistor whose gate terminal is electrically connected to the selection line,

wherein the first to m-th memory cells each comprise;

a first transistor comprising a first gate terminal, a first source terminal, and a first drain terminal;

a second transistor comprising a second gate terminal, a second source terminal, and a second drain terminal; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the source line is electrically connected to the first source terminal in the m-th memory cell through the selection transistor,

wherein the bit line is electrically connected to the second drain terminal in the first memory cell and is electrically connected to the first drain terminal in the first memory cell,

wherein the k-th (k is a natural number greater than or equal to 1 and less than or equal to m) signal line is electrically connected to the second gate terminal in the k-th memory cell,

wherein the k-th word line is electrically connected to one terminal of the capacitor in the k-th memory cell,

wherein the second drain terminal in the l-th (l is a natural number greater than or equal to 2 and less than or equal to m) memory cell is electrically connected to the first gate terminal in the (l−

1)-th memory cell, the second source terminal in the (l−

1)-th memory cell, and the other terminal of the capacitor in the (l−

1)-th memory cell,

wherein the first gate terminal in the m-th memory cell, the second source terminal, in the m-th memory cell, and the other terminal of the capacitor in the m-th memory cell are electrically connected to one another, and

wherein the first drain terminal in the l-th memory cell is electrically connected to the first source terminal in the (l−

1)-th memory cell.

2. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region provided in a substrate including a semiconductor material;

impurity regions provided so that the channel formation region is sandwiched between the impurity regions;

a first gate insulating layer over the channel formation region; and

a first gate electrode provided over the first gate insulating layer so as to overlap with the channel formation region, and

wherein the second transistor comprises;

a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer;

a second gate electrode provided over the oxide semiconductor layer; and

a second gate insulating layer provided between the oxide semiconductor layer and the second gate electrode.

3. The semiconductor device according to claim 2,

wherein the second drain electrode in the l-th memory cell and the second source electrode in the (l−

1)-th memory cell are formed from the same conductive layer.

4. The semiconductor device according to claim 2,

wherein the second drain electrode in the l-th memory cell, the second source electrode in the (l−

1)-th memory cell, and the first gate electrode in the (l−

1)-th memory cell are formed from the same conductive layer.

5. The semiconductor device according to claim 2,

wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

6. The semiconductor device according to claim 2,

wherein the semiconductor material is silicon.

7. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer includes an oxide semiconductor material containing In, Ga, and Zn.

8. A semiconductor device comprising:

a source line;

a bit line;

m (m is an integer greater than or equal to

     2) signal lines;

m word lines;

a first selection line;

a second selection line;

first to m-th memory cells connected in series between the source line and the bit line;

a first selection transistor whose gate terminal is electrically connected to the first selection line; and

a second selection transistor whose gate terminal is electrically connected to the second selection line,

wherein the first to m-th memory cells each comprise;

a first transistor comprising a first gate terminal, a first source terminal, and a first drain terminal;

a second transistor comprising a second gate terminal, a second source terminal, and a second drain terminal; and

a capacitor,

wherein the second transistor includes an oxide semiconductor layer,

wherein the source line is electrically connected to the first source terminal in the m-th memory cell through the second selection transistor,

wherein the bit line is electrically connected to the second drain terminal in the first memory cell, and is electrically connected to the first drain terminal in the first memory cell through the first selection transistor,

wherein the k-th (k is a natural number greater than or equal to 1 and less than or equal to m) signal line is electrically connected to the second gate terminal in the k-th memory cell,

wherein the k-th word line is electrically connected to one terminal of the capacitor in the k-th memory cell,

wherein the second drain terminal, in the l-th (l is a natural number greater than or equal to 2 and less than or equal to m) memory cell is electrically connected to the first gate terminal in the (l−

1)-th memory cell, the second source terminal in the (l−

1)-th memory cell, and the other terminal of the capacitor in the (l−

1)-th memory cell,

wherein the first gate terminal in the m-th memory cell, the second source terminal in the m-th memory cell, and the other terminal of the capacitor in the m-th memory cell are electrically connected to one another, and

wherein the first drain terminal in the l-th memory cell is electrically connected to the first source terminal in the (l−

1)-th memory cell.

9. The semiconductor device according to claim 8,

wherein the first transistor comprises;

a channel formation region provided in a substrate including a semiconductor material;

impurity regions provided so that the channel formation region is sandwiched between the impurity regions;

a first gate insulating layer over the channel formation region; and

a first gate electrode provided over the first gate insulating layer so as to overlap with the channel formation region, and

wherein the second transistor comprises;

a second, source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer;

a second gate electrode provided over the oxide semiconductor layer; and

a second gate insulating layer provided between the oxide semiconductor layer and the second gate electrode.

10. The semiconductor device according to claim 9,

wherein the second drain electrode in the l-th memory cell and the second source electrode in the (l−

1)-th memory cell are formed from the same conductive layer.

11. The semiconductor device according to claim 9,

wherein the second drain electrode in the l-th memory cell, the second source electrode in the (l−

1)-th memory cell, and the first gate electrode in the (l−

1)-th memory cell are formed from the same conductive layer.

12. The semiconductor device according to claim 9,

wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

13. The semiconductor device according to claim 9,

wherein the semiconductor material is silicon.

14. The semiconductor device according to claim 8,

wherein the oxide semiconductor layer includes an oxide semiconductor material containing In, Ga, and Zn.