MOSFET device with thick trench bottom oxide

• US 8,598,654 B2
• Filed: 03/16/2011
• Issued: 12/03/2013
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Park, Chanho, Challa, Ashok, Sodhi, Ritu
• Primary Examiner(s): Swanson, Walter H
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US13/049,629
• Publication Number:
  US 20120235230A1
• Time in Patent Office: 993 Days
• Field of Search: 257/331, 257/330, 257/329, 257/327, 257/288, 257/213, 257/335, 257/341, 438/269, 438/270
• US Class Current: 257/333
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench.

Claims

1. An apparatus, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a first trench within the epitaxial layer;

a trench oxide disposed within the first trench and having a trench bottom oxide portion disposed below a gate portion of the trench oxide, the trench bottom oxide excluding a shield electrode; and

a second trench disposed lateral to the first trench, the trench bottom oxide of the trench oxide having a thickness greater than a distance within the epitaxial layer between the first trench and the second trench, the epitaxial layer having a portion disposed between a bottom surface of the first trench and the substrate.

2. The apparatus of claim 1, wherein the second trench includes a trench oxide having a trench bottom oxide portion, the trench bottom oxide portion of the trench oxide of the first trench and the trench bottom oxide portion of the trench oxide of the second trench collectively have a charge density configured to deplete the epitaxial layer along an entirety of the distance when the apparatus is in an off state.

3. The apparatus of claim 1, wherein the first trench defines at least a portion of a metal-oxide-semiconductor field effect transistor (MOSFET) device, and the epitaxial layer is depleted along an entirety of the distance between the first trench and the second trench when the MOSFET device is in an off state.

4. The apparatus of claim 1, wherein the thickness of the trench bottom oxide portion of the trench oxide is more than two times the distance between the first trench and the second trench.

5. The apparatus of claim 1, further comprising:

a gate electrode disposed within the first trench above the trench bottom oxide portion and substantially lateral to the gate portion of the trench oxide; and

a drain contact disposed below the first trench and the second trench.

6. The apparatus of claim 1, wherein the epitaxial layer has a first conductivity type,

the apparatus further comprising:

a gate electrode disposed within the first trench above the trench bottom oxide portion and substantially lateral to the gate portion of the trench oxide; and

a body region disposed above the epitaxial layer and disposed between the gate portion of the trench oxide disposed within the first trench and a gate portion of a trench oxide disposed within the second trench, the body region having a second conductivity type different from the first conductivity type, the body region configured to convey current from the body region to the epitaxial layer when a channel is formed in the body region in response to a voltage being applied to the gate electrode.

7. The apparatus of claim 1, wherein the trench bottom oxide portion has an output capacitance that is smaller than a gate capacitance if the trench bottom oxide portion includes a shield electrode.

8. The apparatus of claim 1, further comprising:

a gate electrode disposed within the trench, gate electrode having a portion with a substantially flat bottom surface, the thickness of the trench oxide is approximately between the bottom surface of the gate electrode and the bottom surface of the trench oxide.

9. An apparatus, comprising:

a substrate;

a first trench including a first trench oxide having a portion disposed below a center portion of a first gate electrode, the first trench oxide excluding a shield electrode;

a second trench including a second trench oxide having a portion disposed below a second gate electrode; and

an epitaxial layer disposed on the substrate and having a portion extending from the first trench oxide to the second trench oxide, the portion of the first trench oxide having a thickness greater than a width of the portion of the epitaxial layer extending from the first trench oxide to the second trench oxide, the epitaxial layer having a portion disposed between a portion of a bottom surface of the first trench and the substrate.

10. The apparatus of claim 9, further comprising:

a body region disposed between the first trench oxide and the second trench oxide; and

a junction defined by an interface of the epitaxial layer and the body region, the second trench oxide being aligned along an axis substantially orthogonal to the junction.

11. The apparatus of claim 9, wherein the thickness of the portion of the first trench oxide is between a bottom surface of the gate electrode and a bottom surface of the portion of the first trench oxide, the first gate electrode has a portion with a substantially flat bottom surface.

12. The apparatus of claim 9, wherein the thickness of the portion of the first trench oxide is more than two times the width of the portion of the epitaxial layer.

13. The apparatus of claim 9, wherein the thickness of the first trench oxide is less than three times the width of the portion of the epitaxial layer.

14. The apparatus of claim 9, wherein the portion of the first trench oxide is configured to offset a charge within the portion of the epitaxial layer.

15. The apparatus of claim 9, wherein the epitaxial layer has a first conductivity type,

the apparatus further comprising:

a body region disposed above the epitaxial layer and disposed between the first gate electrode and the second gate electrode, the body region having a second conductivity type, the body region configured to convey current from the body region to the epitaxial layer when a channel is formed in the body region in response to the first gate electrode being activated.

16. An apparatus, comprising:

a substrate;

an epitaxial layer disposed on the substrate;

a first trench disposed in the epitaxial layer and including a trench bottom oxide having a portion disposed below a center portion of a gate electrode disposed within the first trench, the trench bottom oxide excluding a shield electrode; and

a second trench lined with a trench oxide,

the epitaxial layer defining

a mesa disposed between the first trench and the second trench, the trench bottom oxide included in the first trench having a thickness greater than a width of the mesa extending between the first trench to the second trench, the epitaxial layer having a portion disposed between a bottom surface of the first trench and the substrate.

17. The apparatus of claim 16, wherein the second trench includes a trench bottom oxide, the trench bottom oxide of the first trench and the trench bottom oxide of the second trench collectively have a charge density configured to deplete the mesa along an entirety of the width.

18. The apparatus of claim 16, wherein the first trench defines at least a portion of a first MOSFET device, and the mesa is depleted along an entirety of the width when the MOSFET device is in an off state.

19. The apparatus of claim 16, wherein the thickness of the trench bottom oxide of the first trench is more than two times the width of the mesa.

20. The apparatus of claim 16, wherein the gate electrode is disposed within the first trench above the trench bottom oxide and substantially lateral to a gate portion of the first trench the apparatus, further comprising:

a drain contact disposed below the first trench and the second trench.

21. The apparatus of claim 16, wherein the gate electrode has a portion with a substantially flat bottom surface, the thickness of the trench bottom oxide is approximately between the bottom surface of the gate electrode and the bottom surface of the first trench.