IC with deskewing circuits

• US 8,598,909 B2
• Filed: 02/06/2012
• Issued: 12/03/2013
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/367,351
• Publication Number:
  US 20120200314A1
• Time in Patent Office: 666 Days
• Field of Search: 326 37- 41, 326/46, 326/47, 714/700
• US Class Current: 326/46
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs.

In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to a trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.

Claims

1. A configurable integrated circuit (“

IC”

) comprising;

a set of sampling circuits for continuously providing data related to states of the configurable IC during the IC'"'"'s operation;

a set of capture circuits for storing the data provided by the set of sampling circuits; and

a set of trigger circuits for analyzing the data as the data is being stored by the set of capture circuits and directing the set of capture circuits to stop recording new data when a pre-determined condition has been met, wherein the set of trigger circuits comprise a set of deskew circuits for temporally aligning a subset of the data before the data is analyzed.

2. The configurable IC of claim 1, wherein the set of sampling circuits provides the data by directing elements in one or more configurable tiles of the IC to stream out the data during user design operations of the configurable IC.

3. The configurable IC of claim 2, wherein the data is streamed out at a frequency equal to a frequency of the user design operations.

4. The configurable IC of claim 2, wherein the data is streamed out at a frequency faster than a frequency of the user design operations.

5. The configurable IC of claim 2 further comprising a transport network for transporting the data from the elements to the set of capture circuits.

6. The configurable IC of claim 5, wherein the transport network is further for transporting the subset of the data to the set of deskew circuits.

7. The configurable IC of claim 5, wherein the transport network is further for transporting the data to the set of trigger circuits.

8. The configurable IC of claim 1, wherein the configurable IC is a subcycle reconfigurable IC.

9. A method for debugging an integrated circuit (“

IC”

), the method comprising;

receiving temporally unaligned data, wherein the temporally unaligned data is produced by a plurality of operations performed by a plurality of configurable logic circuits within the IC;

outputting bits of the temporally unaligned data at a plurality of outputs with different delays, wherein outputting the bits of the temporally unaligned data comprises outputting at least one bit of the temporally unaligned data at a plurality of outlets; and

selecting and storing a subset of the bits from the plurality of outputs to temporally align the temporally unaligned data.

10. The method of claim 9, wherein the plurality of configurable logic circuits are subcycle reconfigurable logic circuits.

11. The method of claim 9 further comprising storing a set of data produced by the plurality of operations into a trace buffer, wherein the set of data comprises the temporally unaligned data.

12. The method of claim 11, wherein the set of data is transported to the trace buffer by a transport network.

13. The method of claim 12, wherein the bit of the temporally unaligned data is received from an output of the transport network.

14. The method of claim 11, wherein the set of data relates to states of the plurality of configurable logic circuits during the plurality of operations.

15. The method of claim 11 further comprising analyzing the temporally unaligned data.

16. The method of claim 15 further comprising directing the trace buffer to stop recording new data when a pre-determined condition has been met based on result of the analyzing.

17. A non-transitory machine readable medium storing a program that configures a set of monitoring circuits of an integrated circuit (“

IC”

) comprising a plurality of configurable logic circuits to monitor an implementation of an IC design in the IC, the program executable by at least one processor, the program comprising sets of instructions for;

configuring a transport network to receive temporally unaligned data, wherein the temporally unaligned data is produced by a plurality of operations performed by the plurality of configurable logic circuits; and

configuring a set of deskew circuits to;

output bits of the temporally unaligned data at a plurality of outputs with different delays, wherein outputting the bits of the temporally unaligned data comprises outputting at least one bit at a plurality of outlets; and

select and store the bits of the temporally unaligned data from the plurality of outputs to temporally align the temporally unaligned data.

18. The non-transitory machine readable medium of claim 17, wherein the program further comprises a set of instructions for configuring the transport network to transport a set of data produced by the plurality of operations into a trace buffer, wherein the set of data comprises the temporally unaligned data.

19. The non-transitory machine readable medium of claim 18, wherein the program further comprises a set of instructions for configuring a trigger circuit to:

analyze the temporally unaligned data after the deskew circuits temporally align the temporally unaligned data; and

direct the trace buffer to stop recording new data when a pre-determined condition has been met.