Display panel

• US 8,599,181 B2
• Filed: 09/07/2011
• Issued: 12/03/2013
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lin, Yu-Min, Chen, Hsin-Li, Gan, Feng-Yuan
• Primary Examiner(s): Sharifi-Tafreshi, Koosha
• Application Number:
  US13/227,455
• Publication Number:
  US 20110316830A1
• Time in Patent Office: 818 Days
• Field of Search: 345/207, 345/173, 345/175, 356/3.06, 257/462, 257/59, 257/72, 257/83, 257/84, 257/292, 257/432, 257/290, 257/291, 257/431, 257/461, 257/444, 257/440, 349/116
• US Class Current: 345/207
• CPC Class Codes: G02F 1/13312 Circuits comprising photodetectors for purposes other than feedback
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2360/144 the light being ambient light
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 31/12 structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto semiconductor devices with at least one potential barrier or surface barrier adapted for light emission H01L33/00; amplifiers using electroluminescent element and photocell H03F17/00; electroluminescent light sources per se H05B33/00
• CPC Class Codes: H01L 31/145 the semiconductor device sensitive to radiation being characterised by at least one potential-jump barrier or surface barrier
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A photo detector is disclosed. The photo detector includes a substrate, a first patterned semiconductor layer, a dielectric layer, a patterned conductive layer, an inter-layer dielectric, a second patterned semiconductor layer, two first electrodes disposed on the inter-layer dielectric and two second electrodes disposed on portions of the second semiconductor layer. The first patterned semiconductor layer having a first doping region and a second doping region is disposed on a transistor region. The dielectric layer is disposed to cover the substrate and the first semiconductor layer, the patterned conductive layer is disposed on the dielectric layer, and the inter-layer dielectric having at least two openings adapted to expose the first doping region and the second doping region is disposed to cover the dielectric layer. The second patterned semiconductor layer is disposed on a photosensitive region and the first electrodes are electrically connected to the first patterned semiconductor layer.

Claims

1. A display panel, having a display area and a non-display area, comprising:

a plurality of pixels disposed in the display area;

at least one driving circuit electrically connected to the pixels; and

at least one photosensitive region having at least one photo detector electrically connected to the at least one driving circuit, the at least one photo detector, comprising;

a substrate having a transistor region and a photosensitive region;

a first patterned semiconductor layer disposed on the transistor region of the substrate, wherein the first patterned semiconductor layer comprises a first doping region and a second doping region;

a dielectric layer covering the first patterned semiconductor layer of the transistor region, the photosensitive region, and the substrate;

a first patterned conductive layer formed on the dielectric layer of the transistor region and on the dielectric layer of the photosensitive region;

an interlayer dielectric layer covering the dielectric layer and the first patterned conductive layer, wherein the interlayer dielectric layer comprises at least two openings to expose a portion of the first doping region of the first patterned semiconductor layer and a portion of the second doping region of the first patterned semiconductor layer;

a second patterned semiconductor layer disposed on the interlayer dielectric layer of the photosensitive region;

two first electrodes formed on the interlayer dielectric layer and electrically connected with the first patterned semiconductor layer via the at least two openings respectively; and

two second electrodes formed on the portion of the second patterned semiconductor layer.

2. The display panel of claim 1, wherein the first patterned semiconductor layer has a first crystal state, the second patterned semiconductor layer has a second crystal state, and the first crystal state is different from the second crystal state.

3. The display panel of claim 1, further comprising a patterned passivation layer covering the interlayer dielectric layer and the first and the second electrodes.

4. The display panel of claim 3, further comprising a second patterned conductive layer having a first potion and a second portion formed on the patterned passivation layer of the transistor region and the patterned passivation layer of the photosensitive region, wherein the first portion is electrically connected to one of the first electrodes of the transistor region and the second portion is substantially disposed between the two second electrodes of the photosensitive region.

5. The display panel of claim 4, wherein the edge of one of the two second electrodes and an edge of the second portion are separated by a first distance and the edge of the other one of the two second electrodes and the other edge of the second portion are separated by a second distance.

6. The display panel of claim 5, wherein the ratio between the first distance and the second distance is 0 to about 7.5.

7. The display panel of claim 4, wherein the second portion is electrically connected to a voltage source.

8. The display panel of claim 4, wherein the second portion is electrically connected to at least one of the patterned conductive layers of the photosensitive region and one of the second electrodes.

9. The display panel of claim 1, further comprising at least one storage capacitor electrically connected to one of the first electrodes of the transistor region.

10. The display panel of claim 1, comprising:

a sensing circuit electrically connected to one of the two electrodes of the at least one photo detector within the at least photosensitive region, a first signal source, a second signal source, and a first voltage source;

an amplifier having two inputs electrically connected to one of the two electrodes of the at least one photo detector within the at least one photosensitive region and a reference voltage, and an output electrically connected to the driving circuit; and

a first transistor having a source/drain electrode electrically connected to one of the two inputs of the amplifier, another source/drain electrode electrically connected to the driving circuit, and a gate electrode electrically connected to a reset signal source.

11. The display panel of claim 1, wherein the at least one photosensitive region is disposed within at least portion of the pixels of the display area.

12. The display panel of claim 11, further comprising:

a sensing circuit disposed within at least one portion of the pixels and electrically connected to at least one select line, a first voltage source, at least one amplifier, and one of the two electrodes of the at least one photo detector within the at least one photosensitive region;

a first transistor disposed within each one of the pixels, wherein the first transistor comprises a source electrode, a gate electrode electrically connected to one data line, and a drain electrode electrically connected to a scan line, and

at least one capacitor electrically connected to the first transistor.