Semiconductor memory device and driving method thereof

• US 8,599,604 B2
• Filed: 10/19/2011
• Issued: 12/03/2013
• Est. Priority Date: 10/25/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US13/276,351
• Publication Number:
  US 20120099360A1
• Time in Patent Office: 776 Days
• Field of Search: 365/154, 365/205, 365/72
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

In a memory cell, a transistor with extremely high off-resistance is used as a write transistor; a drain and a source of the write transistor are connected to a write bit line and an input of an inverter, respectively; and a drain and a source of a read transistor are connected to a read bit line and an output of the inverter, respectively. Capacitors may be intentionally disposed to the source of the write transistor. Alternatively, parasitic capacitance may be used. Since the data retention is performed using charge stored on these capacitors, a potential difference between power sources for the inverter can be 0. This eliminates leakage current between the positive and negative electrodes of the inverter, thereby reducing power consumption.

Claims

1. A semiconductor memory device comprising:

one or more bit lines;

one or more write word lines;

one or more read word lines;

one or more memory cells; and

a first inverter,

wherein each of the memory cells comprises a write transistor, a read transistor, and a second inverter,

wherein a maximum resistance of the write transistor is 1×

10¹⁸Ω

or more,

wherein one of a source and a drain of the write transistor is connected to one of the bit lines,

wherein one of a source and a drain of the read transistor is connected to another of the bit lines,

wherein the other of the source and the drain of the write transistor is connected to an input of the second inverter,

wherein the other of the source and the drain of the read transistor is connected to an output of the second inverter,

wherein a gate of the write transistor is connected to the write word line,

wherein a gate of the read transistor is connected to the read word line,

wherein the one of the bit lines is configured to connected to an input of the first inverter, and

wherein an output of the first inverter is connected to the another of the bit lines.

2. The semiconductor memory device according to claim 1, wherein the other of the source and the drain of the write transistor is connected to one electrode of a capacitor.

3. The semiconductor memory device according to claim 1, wherein the second inverter is a complementary inverter.

4. The semiconductor memory device according to claim 1, wherein conductivity type of the read transistor is different from conductivity type of the write transistor.

5. The semiconductor memory device according to claim 1, wherein the write transistor and the read transistor are disposed in different layers.

6. The semiconductor memory device according to claim 1, wherein the write transistor and one transistor included in the second inverter are disposed in different layers.

7. The semiconductor memory device according to claim 1, wherein semiconductor for the write transistor and semiconductor for the read transistor are of different kinds.

8. The semiconductor memory device according to claim 1, wherein semiconductor for the write transistor and semiconductor for one transistor included in the second inverter are of different kinds.

9. A method of driving the semiconductor memory device according to claim 1, wherein a potential difference between positive and negative electrodes of the second inverter is set to 0.1 V or less during a data retention period.

10. A method of driving the semiconductor memory device according to claim 1, wherein, during reading of data, an input potential of the second inverter is higher than a potential of the positive electrode of the second inverter or lower than a potential of the negative electrode of the second inverter.

11. A semiconductor memory device comprising:

a first bit line and a second bit line;

a write word line;

a read word line;

a memory cell; and

a first inverter,

wherein the memory cell comprises a write transistor, a read transistor, and a second inverter,

wherein a maximum resistance of the write transistor is 1×

10¹⁸Ω

or more,

wherein one of a source and a drain of the write transistor is connected to the first bit line,

wherein one of a source and a drain of the read transistor is connected to the second bit line,

wherein the other of the source and the drain of the write transistor is connected to an input of the second inverter,

wherein the other of the source and the drain of the read transistor is connected to an output of the second inverter,

wherein a gate of the write transistor is connected to the write word line,

wherein a gate of the read transistor is connected to the read word line,

wherein the second bit line is configured to connected to an input of the first inverter, and

wherein an output of the first inverter is configured to connected to the first bit line.

12. The semiconductor memory device according to claim 11, wherein the other of the source and the drain of the write transistor is connected to one electrode of a capacitor.

13. The semiconductor memory device according to claim 11, wherein the second inverter is a complementary inverter.

14. The semiconductor memory device according to claim 11, wherein conductivity type of the read transistor is different from conductivity type of the write transistor.

15. The semiconductor memory device according to claim 11, wherein the write transistor and the read transistor are disposed in different layers.

16. The semiconductor memory device according to claim 11, wherein the write transistor and one transistor included in the second inverter are disposed in different layers.

17. The semiconductor memory device according to claim 11, wherein semiconductor for the write transistor and semiconductor for the read transistor are of different kinds.

18. The semiconductor memory device according to claim 11, wherein semiconductor for the write transistor and semiconductor for one transistor included in the second inverter are of different kinds.

19. A method of driving the semiconductor memory device according to claim 11, wherein a potential difference between positive and negative electrodes of the second inverter is set to 0.1 V or less during a data retention period.

20. A method of driving the semiconductor memory device according to claim 11, wherein, during reading of data, an input potential of the second inverter is higher than a potential of the positive electrode of the second inverter or lower than a potential of the negative electrode of the second inverter.