Distortion estimation and cancellation in memory devices

• US 8,599,611 B2
• Filed: 09/22/2011
• Issued: 12/03/2013
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Shalvi, Ofir, Sommer, Naftali, Gurgi, Eyal, Maislos, Ariel
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/239,408
• Publication Number:
  US 20120026788A1
• Time in Patent Office: 803 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.09, 711/103, 714/721, 714/774
• US Class Current: 365/185.02
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

Claims

1. A method for operating a memory, comprising:

storing data as respective first voltage levels in analog memory cells of the memory, in which a subset of the memory cells has correlative distortion;

after storing the data, reading from one or more of the analog memory cells in the subset respective second voltage levels, which differ from the first voltage levels due to the correlative distortion;

processing the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels;

reading a second voltage level from another analog memory cell in the subset;

predicting a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the subset;

correcting the second voltage level read from the other memory cell using the predicted distortion level; and

reconstructing the data stored in the other memory cell based on the corrected second voltage level;

wherein the stored data is encoded with an Error Correcting Code (ECC), and wherein reconstructing the data comprises modifying a soft ECC metric of the second voltage level and decoding the ECC using the modified soft ECC metric.

2. The method according to claim 1, wherein the subset of the memory cells comprises at least one subset type selected from a group of subset types consisting of memory cells located on a common bit line, memory cells located on a common word line, memory cells having common circuitry and memory cells located in proximity to one another.

3. The method according to claim 1, wherein processing the second voltage levels comprises caching only a single value indicative of the distortion levels in the second voltage levels read from the one or more of the analog memory cells in the subset, and wherein predicting the distortion level comprises calculating the predicted distortion level based on the cached single value.

4. The method according to claim 1, wherein predicting the distortion comprises tracking distortion parameters common to the subset of the memory cells and storing the distortion parameters in a data structure.

10. The method according to claim 1, wherein predicting the distortion level comprises predicting a Back Pattern Dependency (BPD) impairment, and wherein correcting the second voltage level comprises correcting the BPD.

11. The method according to claim 1, wherein reading the second voltage levels comprises sensing the second voltage levels using a sense amplifier, and wherein predicting the distortion level and correcting the second voltage level comprise correcting an impairment caused by the sense amplifier.

5. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes multiple analog memory cells, of which a subset of the memory cells has correlative distortion; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data as respective first voltage levels in the analog memory cells, to read from one or more of the analog memory cells in the subset, after storing the data, respective second voltage levels, which differ from the first voltage levels due to the correlative distortion, to process the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels, to read a second voltage level from another analog memory cell in the subset, to predict a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the subset, to correct the second voltage level read from the other memory cell using the predicted distortion level, and to reconstruct the data stored in the other memory cell based on the corrected second voltage level;

wherein the stored data is encoded with an Error Correcting Code (ECC), and wherein the MSP is arranged to modify a soft ECC metric of the second voltage level and to decode the ECC using the modified soft ECC metric, so as to reconstruct the data.

6. The apparatus according to claim 5, wherein the subset of the memory cells comprises at least one subset type selected from a group of subset types consisting of memory cells located on a common bit line, memory cells located on a common word line, memory cells having common circuitry and memory cells located in proximity to one another.

7. The apparatus according to claim 5, wherein the MSP is arranged to cache only a single value indicative of the distortion levels in the second voltage levels read from the one or more of the analog memory cells in the subset, and to calculate the predicted distortion level based on the cached single value.

8. The apparatus according to claim 5, wherein the MSP is arranged to track distortion parameters common to the subset of the memory cells and to store the distortion parameters in a data structure.

12. The apparatus according to claim 5, wherein the predicted distortion level comprises a Back Pattern Dependency (BPD) impairment, and wherein the MSP is arranged to correct the BPD by correcting the second voltage level.

13. The apparatus according to claim 5, wherein the second voltage levels are sensed using a sense amplifier, and wherein the MSP is arranged to correct an impairment caused by the sense amplifier by correcting the second voltage level.

9. A data storage apparatus, comprising:

a memory, which comprises multiple analog memory cells, of which a subset of the memory cells has correlative distortion; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data as respective first voltage levels in a group of the analog memory cells, to read from one or more of the analog memory cells in a column of the array, after storing the data, respective second voltage levels, which differ from the first voltage levels due to a distortion, to process the second voltage levels read from the one or more of the analog memory cells in order to estimate respective distortion levels in the second voltage levels, to read a second voltage level from another analog memory cell in the column, to predict a distortion level in the second voltage level read from the other analog memory cell based on the estimated respective distortion levels of the one or more of the analog memory cells in the column, to correct the second voltage level read from the other memory cell using the predicted distortion level, and to reconstruct the data stored in the other memory cell based on the corrected second voltage level;

wherein the stored data is encoded with an Error Correcting Code (ECC), and wherein the MSP is arranged to modify a soft ECC metric of the second voltage level and to decode the ECC using the modified soft ECC metric, so as to reconstruct the data.