Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data

• US 8,599,612 B2
• Filed: 12/04/2012
• Issued: 12/03/2013
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Liu, David K. Y., Gross, John Nicholas
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/693,965
• Publication Number:
  US 20130128674A1
• Time in Patent Office: 364 Days
• Field of Search: 365/185.03, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A method of operating a non-volatile programmable (NVP) device situated on a substrate comprising:

programming an NPV device including a floating gate, the floating gate comprised of a layer and material that is shared by gates of at least some other non-NVP devices on said substrate,

to a first state with channel hot electrons that alter a voltage threshold of the floating gate,

wherein said channel hot electrons are provided by one of a variable number of drain regions of the NPV device being capacitively coupled to said floating gate based on a variable program voltage;

reading the first state in the NVP device using a bias current to detect said voltage threshold; and

erasing the NVP device with band-band tunneling hot hole injection.

2. A method of operating a programmable non-volatile device comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with at least one of a logic gate or a volatile memory;

providing a source region; and

providing a drain region including at least a first drain region and a second separate drain region; and

capacitively coupling a variable portion of said gate to said drain based on selectively coupling either or both of said first drain region and said second separate drain region;

providing a programming voltage to said drain region, wherein a substantial portion of said programming voltage is also imparted to said floating gate through said capacitive coupling and in an amount corresponding to said selective coupling.

3. A method of operating a multi-level programmable non-volatile device comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with at least one of a logic gate or a volatile memory;

providing a source region; and

providing a drain region including at least a first drain region and a second separate drain region; and

capacitively coupling a variable portion of said gate to said drain based on selectively coupling either or both of said first drain region and said second separate drain region;

providing a variable programming voltage to said drain region, wherein a substantial portion of said variable programming voltage is also imparted to said floating gate through said capacitive coupling and in an amount corresponding to said selective coupling;

wherein said floating gate is adapted to store multiple levels of charge corresponding to said variable programming voltage.