Three-dimensional NAND memory with stacked mono-crystalline channels

• US 8,599,616 B2
• Filed: 02/02/2012
• Issued: 12/03/2013
• Est. Priority Date: 02/02/2012
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Roizin, Yakov, Strum, Avi
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US13/365,225
• Publication Number:
  US 20130051150A1
• Time in Patent Office: 670 Days
• Field of Search: 438/211, 438/479, 438/591, 438/264, 438/705, 438/738, 438/739, 438/752, 438/753, 438/761, 438/763, 257/E21.18, 257/E27.103, 257/E29.309, 257/E21.09, 257/E21.645, 257/E29.255, 365/185.17
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell'"'"'s channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams. The 3D NVM array effectively includes multiple NVM NAND string structures, where each NAND string structure is formed by multiple series-connected NVM memory cells disposed along an associated bitline structure.

Claims

1. A three-dimensional (3D) non-volatile memory (NVM) array comprising:

a plurality of parallel, spaced-apart horizontally-disposed bitline structures that are arranged in a vertical stack, wherein an air-filled gap is defined between each adjacent pair of bitline structures in the vertical stack, and wherein each said bitline structure includes;

a mono-crystalline silicon beam;

a charge storage layer disposed on said mono-crystalline silicon beam, said charge storage layer comprising a first oxide layer that entirely covers said mono-crystalline silicon beam, and includes a charge trapping material disposed on said first oxide layer; and

a plurality of vertically-disposed conductive posts disposed next to the stack such that each said post contacts substantially only a side portion of a corresponding charge storage layer of each of the charge storage layers disposed on each bitline structure.

2. The 3D NVM array of claim 1,

wherein the first oxide layer of said charge storage layer formed on each of the plurality of beams comprises thermal oxide, and

wherein the charge trapping material disposed on said thermal oxide layer of each of the plurality of beams comprises one of silicon-nitride, nano-dots and Hf_xAl_yO_z.

3. The 3D NVM array of claim 2,

wherein each said charge storage layer formed on each of the plurality of beams further comprises a second oxide/dielectric layer disposed on the charge trapping layer, and

wherein each of the plurality of vertically-disposed conductive posts disposed next to the stack contacts the second oxide/dielectric layer of each said charge storage layer such that an NVM cell is formed at the intersection of each said post and each said bitline structure.

4. The 3D NVM array of claim 1, wherein each of the plurality of vertically-disposed conductive posts comprise one of poly-crystalline silicon, Titanium Nitride (TiN) and Tantalum-Nitride (TaN).

5. The 3D NVM array of claim 1, further comprising first means for applying an associated wordline voltage onto each of the plurality of posts, and second means for applying bitline voltages onto said beam of each of the plurality of bitline structures during one of a program operation, an erase operation and a read operation.

6. The 3D NVM array of claim 5, wherein said first and second means includes means for individually generating a first potential across a selected said corresponding charge storing layer portion to be read and a second potential across non-selected said corresponding charge storing layer portions such that a current flows along said beam only when said selected corresponding portion retains a sufficiently large residual charge.

7. The 3D NVM array of claim 1, wherein the plurality of vertically-disposed conductive posts comprises:

a first group of said posts disposed on a first side of said stack such that each post of said first group contacts a corresponding said charge storage layer portions of each said beam to form a plurality of first non-volatile memory cells on the first side of each beam; and

a second group of said posts disposed on a second side of said stack such that each post of said second group contacts a corresponding said charge storage layer portions of each said beam to form a plurality of second non-volatile memory cells on the second side of each beam,

wherein each post of said first group is spaced-apart from every post of the second group.

8. The 3D NVM array of claim 1, wherein each bitline structure comprises:

a first section including a first portion of said beam and said charge storage layer disposed on the first portion;

a second section including a second portion of said beam and a dopant diffused into said second portion such that said second portion of said beam is electrically conductive; and

a vertically-disposed conductive select-line structure disposed next to the stack such that each said select-line structure contacts a corresponding portion of each of the charge storage layers, located between the first section and the second section of each said bitline structure in said stack.

9. The 3D NVM array of claim 8, wherein a length of said select-line structure is larger than a length of each of said posts.

10. The 3D NVM array of claim 8, wherein said second sections of each bitline structure in each stack has a different length such that said second sections form a staircase arrangement, and

wherein said 3D NVM array further comprises vertical metal contacts connected to the second portions of each bitline structure in each stack.

11. The 3D NVM array of claim 8, further comprising a protective layer covering the plurality of posts and the plurality of bitline structures.

12. The 3D NVM array of claim 1, further comprising a protective layer covering the plurality of posts and the plurality of bitline structures, wherein the protective layer comprises undoped silicate glass (USG).

14. The NVM NAND string structure of claim 12, wherein the plurality of spaced-apart conductive wordline structures comprise:

a first group of said wordline structures disposed on a first side of said elongated bitline structure such that each wordline structure of said first group contacts a corresponding said charge storage layer portion of said bitline structure to form a plurality of first non-volatile memory cells on the first side of said bitline structure; and

a second group of said wordline structures disposed on a second side of said elongated bitline structure such that each wordline structure of said second group contacts a corresponding said charge storage layer portion of said bitline structure to form a plurality of second non-volatile memory cells on the second side of said bitline structure,

wherein each said wordline structure of the first group is spaced-apart from every said wordline structure of the second group.

13. A non-volatile memory (NVM) NAND string structure comprising:

an elongated bitline structure including;

an elongated mono-crystalline silicon bitline structure having opposing upper and lower surfaces, and opposing side surfaces; and

a charge storage layer disposed on said mono-crystalline silicon beam, said charge storage layer including a thermal oxide layer that forms a continuous layer on the upper, lower and opposing side surfaces of said bitline structure, a charge trapping layer disposed on the thermal oxide layer, and a second oxide/dielectric layer disposed on the charge trapping layer; and

a plurality of spaced-apart conductive wordline structures disposed such that each said post contacts substantially only a side portion of a corresponding portion of the second oxide/dielectric layer of the charge storage layer.

15. A three-dimensional (3D) non-volatile memory (NVM) array comprising:

a plurality of parallel horizontally-disposed elongated bitline structure that are arranged in a plurality of vertical stacks, wherein an air-filled gap is defined between each adjacent pair of bitline structures in each of the plurality of stacks, each of the bitline structures including;

a mono-crystalline silicon beam; and

a charge storage layer disposed on a first portion of said mono-crystalline silicon beam, wherein each said charge storage layer include a first oxide layer that entirely covers said first portion of said associated mono- crystalline silicon beams; and

a plurality of vertically-disposed conductive wordline structures, each said wordline structure being disposed next to at least one stack of said plurality of vertical stacks such that said each wordline structure contacts substantially only a side portion of the corresponding said charge storage layer of each of the bitline structures in said at least one stack.

16. The 3D NVM array of claim 15, wherein the plurality of vertically-disposed conductive wordline structures comprises:

a first group of said wordline structures disposed on a first side of a first said stack such that each wordline structure of said first group contacts a corresponding said charge storage layer portion of each bitline structure in said first stack to form a plurality of first non-volatile memory cells on the first side of said each bitline structure in said first stack; and

a second group of said wordline structures disposed on a second side of said first said stack such that each wordline structure of said second group contacts a corresponding said charge storage layer portion of each bitline structure in said first stack to form a plurality of second non-volatile memory cells on the second side of said each bitline structure in said first stack,

wherein each wordline structure of said first group is spaced-apart from every wordline structure of the second group.

17. The 3D NVM array of claim 15, wherein each bitline structure comprises:

a first section including a first portion of said beam and said charge storage layer disposed on the first portion;

a second section including a second portion of said beam and a dopant diffused into said second portion such that said second portion of said beam is electrically conductive; and

a vertically-disposed conductive select-line structure disposed next to each said stack such that each said select-line structure contacts a corresponding portion of each of the charge storage layers, located between the first section and the second section of each said bitline structure in each said stack.

18. The 3D NVM array of claim 15, wherein the first oxide layer of said charge storage layer formed on each of the plurality of beams comprises thermal oxide, and

wherein the charge trapping material disposed on said thermal oxide layer of each of the plurality of beams comprises one of silicon nitride, nano-dots and Hf_xAl_yO_z.