Circuits and methods for measuring circuit elements in an integrated circuit device

• US 8,599,623 B1
• Filed: 12/23/2011
• Issued: 12/03/2013
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T, Roy, Richard S
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US13/336,434
• Time in Patent Office: 711 Days
• Field of Search: 365/189.02, 365/201, 365/198, 711/30, 711/718, 711/719
• US Class Current: 365/189.02
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An integrated circuit device can include a plurality of test elements, each comprising at least one first switch coupled between a node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and an output node; wherein the forced voltage node is coupled to receive a forced voltage substantially the same as a test voltage applied to the output node in a test mode.

Claims

1. An integrated circuit device, comprising:

a plurality of test elements, each comprising

at least one first switch coupled between a node within a tested section and an intermediate node,

a test switch coupled between the intermediate node and a forced voltage node, and

a second switch coupled between the intermediate node and an output node;

wherein

the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a test voltage applied to the output node.

2. The integrated circuit device of claim 1, wherein:

each test element of the plurality of test elements is operable in a first mode, the at least one first switch being coupled to provide a low impedance path and the test switch being coupled to provide a high impedance path in the first mode; and

each test element of the plurality of test elements is operable in a second mode, the at least one first switch being coupled to provide a high impedance path and the test switch being coupled to provide a low impedance path in the second mode.

3. The integrated circuit device of claim 1, wherein:

the at least one first switch, test switch, and second switch each comprise transistors of different conductivity types having current paths arranged in parallel with one another.

4. The integrated circuit device of claim 1, wherein:

the at least one first switch, test switch, and second switch each comprise at least one transistor; and

each test element fits within no more than three transistor pitches.

5. The integrated circuit device of claim 1, wherein:

the at least one first switch includes a plurality of first parallel switches, each first parallel switch being coupled between a node of the integrated circuit and the intermediate node;

each test element of the plurality of test elements is operable in a first mode, the test switch being coupled to provide a high impedance path in the first mode, at least one parallel switch of the plurality of first parallel switches being coupled to provide a low impedance path in the first mode, and the first parallel switches other than the at least one parallel switch being coupled to provide a high impedance path in the first mode; and

each test element of the plurality of test elements is operable in a second mode, the test switch being coupled to provide a low impedance path and all of the first parallel switches of the test element being coupled to provide a high impedance state in the second mode.

6. The integrated circuit device of claim 1, wherein:

the tested section comprises a memory array;

the test elements are formed in a same integrated circuit substrate having a plurality of conductive input/output (I/O) pads formed thereon for making electrical connections to the integrated circuit device; and

the forced voltage node is coupled to at least one of the I/O pads.

7. The integrated circuit device of claim 1, further including:

the tested section comprises a memory array; and

a plurality of column multiplexer (MUX) circuits coupled between the test elements and corresponding bit lines of the memory array, each column MUX selectively coupling one of a plurality of bit lines to a test element in response to column address data.

8. The integrated circuit device of claim 1, further including:

the tested section comprises a memory array;

a plurality of sense amplifiers configured to amplify electrical signals on bit lines of the memory array to generate read output data; and

each test element further includes the at least one first switch being coupled to the corresponding bit line via a sense amplifier input.

9. The integrated circuit device of claim 1, further including:

the tested section comprises a memory array formed from a plurality of banks, each bank including bit lines;

each test element couples the corresponding bit line to a bank input/output (I/O) node of its corresponding bank; and

a bank select circuit corresponding to each bank that couples the bank I/O node to the output node.

10. The integrated circuit device of claim 2, further including:

the tested section comprises a memory array having a plurality of memory cells coupled to bit lines, each memory cell including

a first pair of pull-up transistors cross-coupled between two storage nodes, and

a pair of access transistors that couple each storage node to a different bit line; and

a word line driver circuit coupled to enable the access transistors in a test mode;

a first one of the test elements is configured to apply a test voltage on a first bit line to a control terminal of one of the first pull-up transistors through a first of the access transistors in the test mode, the first one of the test elements being configured to be operable in the first mode; and

a second one of the test elements is configured to enable a current drawn by the one pull-up transistor to flow through a second bit line and a second of the access transistors in the test mode, the second one of the test elements being configured to be operable in the first mode.

11. The integrated circuit device of claim 10, further including:

each memory cell further includes a second pair of pull-down transistors, cross-coupled between the two storage nodes and source node; and

a source driver circuit that drives the source node to the test voltage in the test mode.

12. The integrated circuit device of claim 1, wherein:

the tested section comprises a memory array having a plurality of memory cells coupled to bit lines, each memory cell including

a pair of pull-up transistors cross-coupled between two storage nodes, and

a pair of access transistors that couple each storage node to a different bit line; and

a word line driver circuit coupled to apply a test voltage to the control terminals of the access transistors in a test mode;

a first one of the test elements is configured to apply an enable voltage to a control terminal of a first of the pull-up transistors through a first bit line and a first of the access transistors in the test mode, the first one of the test elements being configured to be operable in the first mode; and

a second one of the test elements is configured to enable a current drawn by a second of the access transistor to flow a second bit line and the first of the latching transistors in the test mode, the second one of the test elements being configured to be operable in the first mode.

13. An integrated circuit device, comprising:

a plurality of test elements, each comprising

at least one first switch coupled between a node within a memory section and an intermediate node,

a test switch coupled between the intermediate node and a forced voltage node, and

a second switch coupled between the intermediate node and an output node;

wherein

the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a test voltage applied to the output node.

14. The integrated circuit device of claim 13, wherein:

each test element of the plurality of test elements is operable in a first mode, the at least one first switch being coupled to provide a low impedance path and the test switch being coupled to provide a high impedance path in the first mode; and

each test element of the plurality of test elements is operable in a second mode, the at least one first switch being coupled to provide a high impedance path and the test switch being coupled to provide a low impedance path in the second mode.

15. The integrated circuit device of claim 13, further including:

the memory section includes a sense amplifier comprising a pair of sense transistors cross-coupled between two sense nodes;

an isolation circuit configured to electrically isolate the sense nodes from bit lines of a memory cell array;

a first one of the test elements is configured to apply a test voltage to a control terminal of one of the sense transistors; and

a second one of the test elements is configured to enable a current drawn by the one sense transistor in the test mode.

16. The integrated circuit device of claim 13, wherein:

the memory section includes a sense amplifier configured to drive sense nodes to sense voltages in response to a differential voltage across the sense nodes;

an isolation circuit configured to electrically isolate the sense nodes from bit lines of a memory cell array in an offset test mode;

a read circuit that outputs a read value in response to the sense voltage; and

a first and second test elements configured to apply a differential voltage across the two sense nodes.

17. The integrated circuit device of claim 16, further including:

a test circuit configured to provide a sequence of different differential voltages to the first and second test elements in response to read values from the read circuit.

18. The integrated circuit device of claim 13, wherein:

the memory section includes a sense amplifier comprising

a first pair of sense transistors cross-coupled between two sense nodes,

a first enable transistor coupled between the first pair of sense transistors and a first power supply node, and

a first disable transistor coupled between the first pair of sense transistors and a second power supply node;

wherein

control terminals of the first enable and first disable transistor are commonly coupled to a first sense enable signal.

19. The integrated circuit device of claim 18, wherein:

the sense amplifier further includes

a second pair of sense transistors cross-coupled between the two sense nodes and of a different conductivity type than the first pair of sense transistors,

a second enable transistor coupled between the second pair of sense transistors and the second power supply node, and

a first disable transistor coupled between the second pair of sense transistors and the first power supply node;

wherein

control terminals of the second enable and second disable transistor are commonly coupled to a second sense enable signal that is the inverse of the first sense enable signal.

20. The integrated circuit of claim 13, wherein:

the memory section includes a sense amplifier comprising

a first transistor having a control terminal coupled to a first of the sense nodes, and

a second transistor having a control terminal coupled to a second of the sense nodes.

21. The integrated circuit of claim 13, wherein:

a memory section comprises a plurality of memory cells, each memory cell including

a first pair of pull-up transistors cross-coupled between two storage nodes, and

a pair of access transistors that couple each storage node to a different bit line; and

a word line driver circuit coupled to enable the access transistors in a test mode;

the first one of the test elements is further configured to apply a test voltage on a first bit line to a control terminal of one of the first pull-up transistors through a first of the access transistors in a cell test mode; and

the second one of the test elements is configured to enable a current drawn by the one pull-up transistor to flow through a second bit line and a second of the access transistors in the cell test mode.

22. A method, comprising:

in a direct access mode,

enabling a first signal path between a first output node and a tested section that includes an intermediate node; and

in a low leakage cutoff mode,

enabling at least a second signal path between the first output node and the tested section,

disabling the first signal path between the tested section and the intermediate node and between the intermediate node and the first output node, and

driving the first output node and the intermediate node to substantially a same first test voltage.

23. The method of claim 22, further including:

enabling at least a second path includes

enabling a first test signal path from the first output node to the tested section, and

enabling a second test signal path from a second output node to the tested section.

24. The method of claim 23, further including:

maintaining the first output node at the first test voltage;

varying a voltage at the second output node; and

measuring a current flowing through the first output node.

25. The method of claim 24, wherein:

the tested section is a memory section comprising a plurality of memory cells;

the first test signal path includes a first bit line coupled to a memory cell and a control terminal of a transistor under test (TUT) within the memory cell; and

the second signal path includes a second bit line and a current path of the TUT.

26. The method of claim 25, wherein:

each memory cell comprises

a pair of pull-up transistors cross-coupled between storage nodes,

a pair of pull-down transistors cross-coupled between the storage nodes;

access transistors coupled between the storage nodes and the first and second bit lines; and

the TUT is selected from one of the access transistors, one of the pull-up transistors, or one of the pull-down transistors.

27. The method of claim 24, wherein:

the tested section comprises a memory section that includes a first sense node of sense amplifier and a control terminal of a transistor under test (TUT) within the sense amplifier; and

the second signal path includes a second sense node of the sense amplifier and a current path of the TUT.

28. The method of claim 27, wherein:

the sense amplifier comprises at least a first pair of sense transistors cross-coupled between the sense nodes; and

the TUT is one of the sense transistors.

29. The method of claim 27, further including:

isolating the sense nodes from bit lines of the memory section.

30. The method of claim 23, further including:

the tested section comprises a memory section that includes a sense amplifier;

the first test signal path is coupled to a first sense node of a sense amplifier;

the second test signal path is coupled to a second sense node of the sense amplifier;

applying a differential voltage between the first output node and the second output node; and

activating the sense amplifier to generate a sensed data value.

31. The method of claim 30, further including:

altering the applied differential voltage in response to the sensed data value.