Data regeneration apparatus and method for PCI express

• US 8,599,913 B1
• Filed: 08/01/2011
• Issued: 12/03/2013
• Est. Priority Date: 08/01/2011
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: PMC Sierra US Inc (Microchip Technology Incorporated)
• Inventors: Brown, David Alan, Tran, Dzung
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US13/195,685
• Time in Patent Office: 855 Days
• Field of Search: 375229-233, 375/257, 375259-260, 375/285, 375/340, 375/350, 375/219, 375/220, 375/296, 708322-323, 708/300, 333/28.R
• US Class Current: 375/232
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data regeneration device regenerates a digital signal in a low-speed pass-through mode of operation, performs an upstream link equalization procedure on an upstream data link in an equalization mode of operation, performs a downstream link equalization procedure on a downstream data link in the equalization mode of operation, and regenerates the digital signal in a high-speed pass-through mode of operation. The data regeneration device transitions seamlessly from the low-speed pass-through mode of operation to the equalization mode of operation in compliance with a communication protocol. Moreover, the data regeneration device synchronizes completion of the upstream link equalization procedure with completion of the downstream link equalization procedure so that the data regeneration device transitions seamlessly from the equalization mode of operation to the high-speed pass-through mode of operation in compliance with the communication protocol.

Claims

1. A data regeneration device for regenerating a digital signal in compliance with a Peripheral Component Interconnect Express (PCIe) protocol, the data regeneration device comprising:

an upstream port for performing an upstream link equalization procedure on an upstream data link in compliance with the PCIe protocol;

a downstream port for performing a downstream link equalization procedure on a downstream data link in compliance with the PCIe protocol, the data regeneration device configured to perform a dual-delay interlocking operation so that the downstream link equalization procedure and the upstream link equalization procedure complete at substantially the same time; and

a routing link coupled to the upstream port and the downstream port for communicating a digital signal between the upstream port and the downstream port.

2. The data regeneration device of claim 1, wherein the PCIe protocol is the PCIe 3.0 protocol and wherein the upstream link equalization procedure includes a Phase 2 in compliance with the PCIe 3.0 protocol for performing a downstream port equalization adjustment operation on the upstream data link, the downstream link equalization procedure includes a Phase 3 in compliance with the PCIe 3.0 protocol for performing an upstream port equalization adjustment operation on the downstream data link, and the dual-delay interlocking operation includes delaying a completion of the Phase 2 of the upstream link equalization procedure until the upstream port equalization adjustment operation in Phase 3 of the downstream link equalization procedure is complete.

3. The data regeneration device of claim 2, wherein the upstream link equalization procedure includes a Phase 3 in compliance with the PCIe 3.0 protocol for performing an upstream port equalization adjustment operation on the upstream data link, and the dual-delay interlocking operation includes delaying a completion of Phase 3 of the downstream link equalization procedure until the Phase 3 of the upstream link equalization procedure is complete.

4. The data regeneration device of claim 3, wherein the upstream port equalization adjustment operation of Phase 3 of the downstream link equalization procedure includes an accelerated evaluation process.

5. The data regeneration device of claim 4, wherein the accelerated evaluation process includes a coarse evaluation operation and a fine evaluation operation, the coarse evaluation includes a continuous-time linear equalization but does not include a decision feedback equalization, and the fine evaluation includes both a continuous-time linear equalization and a decision feedback equalization.

6. The data regeneration device of claim 5, wherein the accelerated evaluation process is performed in less than three milliseconds.

7. The data regeneration device of claim 1, wherein the data regeneration device is further configured to regenerate the digital signal in compliance with the PCIe protocol at a low-speed data rate in a low-speed pass-through mode of operation, transition from the low-speed mode of operation to the equalization mode of operation seamlessly in compliance with the PCIe protocol, transition from the equalization mode of operation to a high-speed pass-through mode of operation in compliance with the PCIe protocol, and regenerate the digital signal in compliance with the PCIe protocol at a high-speed data rate in the high-speed pass-through mode of operation.

8. The data regeneration device of claim 1, wherein the upstream port is further configured to perform the upstream link equalization procedure for increasing a signal quality of a digital signal transmitted through the upstream data link, and wherein the downstream port is further configured to perform the downstream link equalization procedure for increasing a signal quality of a digital signal transmitted through the downstream data link.

9. A data regeneration device for regenerating a digital signal in compliance with a Peripheral Component Interconnect Express (PCIe) 3.0 protocol, the data regeneration device comprising:

an upstream port for performing an upstream link equalization procedure on an upstream data link in compliance with the PCIe 3.0 protocol;

a downstream port for performing a downstream link equalization procedure on a downstream data link in compliance with the PCIe 3.0 protocol, the data regeneration device is configured to perform a dual-delay interlocking operation so that the downstream link equalization procedure and the upstream link equalization procedure complete at substantially the same time; and

a routing link coupled to the upstream port and the downstream port for communicating a digital signal between the upstream port and the downstream port, wherein the data regeneration device is further configured to regenerate the digital signal in compliance with the PCIe 3.0 protocol at a low-speed data rate in a low-speed pass-through mode of operation, transition from the low-speed pass-through mode of operation to the equalization mode of operation seamlessly in compliance with the PCIe 3.0 protocol, transition from the equalization mode of operation to a high-speed pass-through mode of operation in compliance with the PCIe 3.0 protocol, and regenerate the digital signal in compliance with the PCIe protocol at a high-speed data rate in the high-speed pass-through mode of operation.

10. The data regeneration device of claim 9, wherein the upstream link equalization procedure includes a Phase 2 in compliance to the PCIe 3.0 protocol for performing a downstream port equalization adjustment operation on the upstream data link, the downstream link equalization procedure includes a Phase 3 in compliance with the PCIe 3.0 protocol for performing an upstream port equalization adjustment operation on the downstream data link, and the data regeneration device is further configured to perform the dual-delay interlocking operation by delaying a completion of the Phase 2 of the upstream link equalization procedure until the upstream port equalization adjustment operation in Phase 3 of the downstream link equalization procedure is complete and by delaying a completion of the Phase 3 of the downstream link equalization procedure until a Phase 3 of the upstream link equalization procedure is complete.

11. The data regeneration device of claim 10, wherein the upstream port equalization adjustment operation of Phase 3 of the downstream link equalization procedure includes an accelerated evaluation process.

12. The data regeneration device of claim 11, wherein the accelerated evaluation process includes a coarse evaluation operation and a fine evaluation operation, the coarse evaluation includes a continuous-time linear equalization but does not include a decision feedback equalization, and the fine evaluation operation includes both a continuous-time linear equalization and a decision feedback equalization.

13. The data regeneration device of claim 12, wherein the accelerated evaluation process is performed in less than three milliseconds.

14. The data regeneration device of claim 9, wherein the downstream port is further configured to perform the downstream link equalization procedure for increasing a signal quality of a digital signal transmitted through the downstream data link, and wherein the upstream port is further configured to perform the upstream link equalization procedure for increasing a signal quality of a digital signal transmitted through the upstream data link.

15. A method of regenerating a digital signal in compliance with a Peripheral Component Interconnect Express (PCIe) protocol, the method comprising:

performing an upstream link equalization procedure on an upstream data link in compliance with the PCIe protocol;

performing a downstream link equalization procedure on a downstream data link in compliance with the PCIe protocol; and

performing a dual-delay interlocking operation so that the downstream link equalization procedure and the upstream link equalization procedure complete at substantially the same time.

16. The method of claim 15, wherein the PCIe protocol is a PCIe 3.0 protocol and wherein the upstream link equalization procedure includes a Phase 2 in compliance with the PCIe 3.0 protocol for performing a downstream port equalization adjustment operation on the upstream data link, the downstream link equalization procedure includes a Phase 3 in compliance with the PCIe 3.0 protocol for performing an upstream port equalization adjustment operation on the downstream data link, and performing the dual-delay interlocking operation includes delaying a completion of the Phase 2 of the upstream link equalization procedure until the upstream port equalization adjustment operation in Phase 3 of the downstream link equalization procedure is complete.

17. The method of claim 16, wherein the upstream link equalization procedure includes a Phase 3 in compliance with the PCIe 3.0 protocol for performing an upstream port equalization adjustment operation on the upstream data link, and performing the dual-delay interlocking operation includes delaying a completion of Phase 3 of the downstream link equalization procedure until the Phase 3 of the upstream link equalization procedure is complete.

18. The method of claim 17, wherein the upstream port equalization adjustment operation includes an accelerated evaluation process including a coarse evaluation operation and a fine evaluation operation, the coarse evaluation operation includes performing a continuous-time linear equalization but does not include performing a decision feedback equalization, and the fine evaluation includes performing both a continuous-time linear equalization and a decision feedback equalization.

19. The method of claim 15, further comprising:

transmitting the digital signal between the upstream port and the downstream port in compliance with the PCIe 3.0 protocol at the low-speed data rate in a low-speed pass-through mode of operation;

transitioning from the low-speed mode of operation to an equalization mode of operation seamlessly in compliance with the PCIe protocol;

performing both the upstream link equalization procedure and the downstream link equalization procedure in the equalization mode of operation;

transitioning from the equalization mode of operation to a high-speed mode of operation seamlessly in compliance with the PCIe protocol; and

transmitting the digital signal between the upstream port and the downstream port in compliance with the PCIe protocol at the high-speed data rate in the high-speed pass-through mode of operation.