Simulating a refresh operation latency

• US 8,601,204 B2
• Filed: 07/13/2011
• Issued: 12/03/2013
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/181,716
• Publication Number:
  US 20120008436A1
• Time in Patent Office: 874 Days
• Field of Search: 711/103, 711/104, 711/105, 711/110, 365/222
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory apparatus includes multiple memory circuits an interface circuit having one or more first components of a first type and one or more second components of a second type different from the first type, each of the one or more first components and second components being electrically couplable to a host system. The interface circuit is operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits. The at least one aspect includes a timing that relates to a refresh operation latency, in which each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component and to at least one second component.

Claims

1. A memory apparatus for use with a host system, the memory apparatus comprising:

a plurality of memory circuits; and

an interface circuit including;

one or more first components of a first type, each of the one or more first components being electrically couplable to the host system; and

one or more second components of a second type different from the first type, each of the one or more second components being electrically couplable to the host system, the interface circuit being operable to present to the host system a simulated memory circuit where there is a difference in at least one aspect between the simulated memory circuit and at least one memory circuit of the plurality of memory circuits, the at least one aspect comprising a timing that relates to a refresh operation latency,

wherein each memory circuit of the plurality of memory circuits is electrically coupled to at least one first component of the one or more first components and to at least one second component of the one or more second components.

2. The memory apparatus of claim 1, where the first type of component is a register and the second type of component is a buffer chip.

3. The memory apparatus of claim 1, where at least one component of the first and second components is operable to receive control and clock signals intended for the simulated memory circuit.

4. The memory apparatus of claim 1, where at least one component of the first and second components is operable to receive data signals intended for the simulated memory circuit.

5. The memory apparatus of claim 1, where the plurality of memory circuits comprise a stack of dynamic random access memory (DRAM) circuits and are coupled to a dual inline memory module (DIMM).

6. The memory apparatus of claim 5, where the DIMM is a registered DIMM (R-DIMM).

7. The memory apparatus of claim 5, where the stack further includes the one or more second components of the second type.

8. The memory apparatus of claim 5, further comprising:

a first package including the one or more second components; and

a second separate package including the plurality of memory circuits.

9. The memory apparatus of claim 5, where the one or more second components are packaged together with the plurality of memory circuits in the stack.

10. The memory apparatus of claim 1, where at least one component of the first and second components is operable to refresh the plurality of physical memory circuits in response to receiving from the host system a first refresh control signal intended for the simulated memory circuit.

11. The memory apparatus of claim 10, where the at least one component of the first and second components is operable to receive the first refresh control signal intended for the simulated memory circuit from a memory controller of the host system.

12. The memory apparatus of claim 10, where the at least one component of the first and second components is operable to minimize a current draw of the plurality of memory circuits by issuing second refresh control signals at different times to one or more memory circuits of the plurality of memory circuits.

13. The memory apparatus of claim 10, where the at least one component of the first and second components is operable to issue a plurality of second refresh control signals to one or more memory circuits of the plurality of memory circuits in response to receiving the first refresh control signal intended for the simulated memory circuit.

14. The memory apparatus of claim 13, where the at least one component of the first and second components is operable to stagger the issuance of the plurality of second refresh control signals to the one or more memory circuits of the plurality of memory circuits.

15. The memory apparatus of claim 1, where the timing comprises one or more of a row address to column address latency (tRCD), a row precharge latency (tRP), an activate to precharge latency (tRAS), a row cycle time (tRC), a refresh latency (tRFC), or a column address strobe (CAS) latency.

16. The memory apparatus of claim 1, where the simulated memory circuit is associated with a first refresh operation latency and the plurality of memory circuits are associated with a second refresh operation latency, where the first refresh operation latency is longer than the second refresh operation latency.

17. The memory apparatus of claim 1, where the at least one aspect includes a signal associated with a mode register operation.

18. The memory apparatus of claim 1, where the at least one aspect includes a number of banks.

19. The memory apparatus of claim 1, where the difference in at least one aspect is a difference in a number of row-address signals.