Supply margining method and apparatus
First Claim
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1. An apparatus comprising:
- a voltage regulator having first and second voltage regulator domains, the first and second voltage regulator domains to provide first and second power supply voltages respectively; and
a CPU, to be coupled to the voltage regulator, to provide the voltage regulator with a voltage command and to receive the first and second power supply voltages corresponding to the commanded voltage from the voltage regulator, and to receive operating parameter information from the voltage regulator,wherein the CPU is coupled to a controller, the controller operable to determine the allowable voltage command values,wherein the CPU is a multi-core CPU having first and second processor cores integrated on a common semiconductor die,wherein the first and second processor cores receive the first and second power supply voltages respectively from the respective first and second voltage regulator domains,wherein the CPU comprises a logic unit which is operable to;
push operation of the CPU to a maximum operating limit of the voltage regulator;
andpush operation of the CPU to a minimum operating limit of the voltage regulator, and wherein the voltage regulator comprises a master controller to control first and second voltage regulator domains by enabling or disabling cells within the first and second voltage regulator domains,and wherein the controller, which is different from the master controller, is external to the CPU and is operable to cause the CPU to execute a margining routine to determine VID levels for the voltage regulator.
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Abstract
In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.
23 Citations
17 Claims
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1. An apparatus comprising:
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a voltage regulator having first and second voltage regulator domains, the first and second voltage regulator domains to provide first and second power supply voltages respectively; and a CPU, to be coupled to the voltage regulator, to provide the voltage regulator with a voltage command and to receive the first and second power supply voltages corresponding to the commanded voltage from the voltage regulator, and to receive operating parameter information from the voltage regulator, wherein the CPU is coupled to a controller, the controller operable to determine the allowable voltage command values, wherein the CPU is a multi-core CPU having first and second processor cores integrated on a common semiconductor die, wherein the first and second processor cores receive the first and second power supply voltages respectively from the respective first and second voltage regulator domains, wherein the CPU comprises a logic unit which is operable to; push operation of the CPU to a maximum operating limit of the voltage regulator; and push operation of the CPU to a minimum operating limit of the voltage regulator, and wherein the voltage regulator comprises a master controller to control first and second voltage regulator domains by enabling or disabling cells within the first and second voltage regulator domains, and wherein the controller, which is different from the master controller, is external to the CPU and is operable to cause the CPU to execute a margining routine to determine VID levels for the voltage regulator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a memory; a multi-core processor coupled to the memory, the multi-core processor comprising first and second processor cores integrated on a common semiconductor die, wherein the multi-core processor is coupled to a voltage regulator having first and second voltage regulator domains, the first and second voltage regulator domains to provide first and second power supply voltages respectively to the first and second processor cores respectively, and wherein the multi-core processor to provide the voltage regulator with a voltage command and to receive the first and second power supply voltages corresponding to the commanded voltage from the voltage regulator, and to receive operating parameter information from the voltage regulator wherein the multi-core processor comprises a logic unit which is operable to; push operation of the multi-core processor to a maximum operating limit of the voltage regulator; and push operation of the multi-core processor to a minimum operating limit of the voltage regulator, and wherein the voltage regulator comprises a master controller to control first and second voltage regulator domains by enabling or disabling cells within the first and second voltage regulator domains; and a controller, which is different from the master controller, which is external to the multi-core processor and is operable to cause the multi-core processor to execute a margining routine to determine VID levels for the voltage regulator. - View Dependent Claims (16, 17)
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Specification