Thin film transistor array panel
First Claim
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1. A thin film transistor array panel, comprising:
- a substrate;
a gate line formed on the substrate and including a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor;
a data line formed on the semiconductor and including a source electrode, the data line extending substantially in a longitudinal direction in a layout view to intersect the gate line; and
a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor,wherein the channel of the thin film transistor covers both side surfaces of the gate electrode in a width direction of the channel of the thin film transistor, the width direction extending along the longitudinal direction of the data line in the layout view, andwherein opposing sides of the gate line across from each other in the longitudinal direction of the data line in the layout view are covered by the channel of the thin film transistor.
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Abstract
A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.
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Citations
13 Claims
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1. A thin film transistor array panel, comprising:
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a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor; a data line formed on the semiconductor and including a source electrode, the data line extending substantially in a longitudinal direction in a layout view to intersect the gate line; and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode in a width direction of the channel of the thin film transistor, the width direction extending along the longitudinal direction of the data line in the layout view, and wherein opposing sides of the gate line across from each other in the longitudinal direction of the data line in the layout view are covered by the channel of the thin film transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A thin film transistor array panel, comprising:
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a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; and a semiconductor formed on the gate insulating layer, wherein a channel of a thin film transistor comprises a portion of the semiconductor covering both side surfaces of the gate electrode in a width direction of the channel of the thin film transistor and the upper surface of the gate electrode, the width direction extending along a longitudinal direction of a data line in a layout view, and wherein opposing sides of the gate line across from each other in the longitudinal direction of the data line in the layout view are covered by the channel of the thin film transistor. - View Dependent Claims (9, 10)
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11. A thin film transistor array panel, comprising:
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a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor; a data line formed on the semiconductor and including a source electrode, the data line extending substantially in a longitudinal direction in a layout view to intersect the gate line; and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein a width of the channel of the thin film transistor is increased by the width of both side surfaces of the gate electrode in a width direction of the channel of the thin film transistor, the width direction extending along the longitudinal direction of the data line in the layout view, and wherein opposing sides of the gate line across from each other in the longitudinal direction of the data line in the layout view are covered by the channel of the thin film transistor. - View Dependent Claims (12, 13)
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Specification
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Current AssigneeTCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
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Original AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
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InventorsLee, Woo-Geun, Youn, Jae-Hyoung, Kim, Ki-Won, Lee, Young-Wook, Kim, Jong-In
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Primary Examiner(s)Sefer, A.
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Application NumberUS12/464,920Publication NumberTime in Patent Office1,672 DaysField of Search257/43, 257/57, 257/59, 257/72, 438/759US Class Current257/43CPC Class CodesH01L 27/1225 with semiconductor material...H01L 29/7869 having a semiconductor body...H01L 29/78696 characterised by the struct...
