Semiconductor device including memory cell

• US 8,604,476 B2
• Filed: 10/11/2011
• Issued: 12/10/2013
• Est. Priority Date: 11/05/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Shionoiri, Yutaka, Nagatsuka, Shuhei, Yakubo, Yuto, Koyama, Jun
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): NGUYEN, DUY T V
• Application Number:
  US13/270,455
• Publication Number:
  US 20120112191A1
• Time in Patent Office: 791 Days
• Field of Search: 257/57, 257/E29.083
• US Class Current: 257/57
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A data retention period in a semiconductor device or a semiconductor memory device is lengthened. The semiconductor device or the semiconductor memory includes a memory circuit including a first transistor including a first semiconductor layer and a first gate and a second transistor including a second semiconductor layer, a second gate, and a third gate The first semiconductor layer is formed at the same time as a layer including the second gate.

Claims

1. A semiconductor device comprising a memory circuit, the memory circuit comprising:

a first transistor;

a second transistor;

a first layer serving as a channel formation layer of the second transistor;

a second layer formed using the same material and at the same time as the first layer, wherein the second layer is apart from the first layer and serves as a first gate of the first transistor;

a first insulating layer over the first layer and the second layer;

a first conductive layer overlapping with the first layer with the first insulating layer provided therebetween;

a semiconductor layer overlapping with the second layer with the first insulating layer provided therebetween;

a second conductive layer electrically connected to the semiconductor layer;

a third conductive layer electrically connected to the first conductive layer and the semiconductor layer;

a second insulating layer over the semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer overlapping with the semiconductor layer with the second insulating layer provided therebetween, the fourth conductive layer serving as a second gate of the first transistor,

wherein the first conductive layer is provided between the first insulating layer and the third conductive layer.

2. The semiconductor device according to claim 1, wherein the first layer and the second layer contain silicon and the semiconductor layer is an oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the second layer contains an impurity element imparting conductivity.

4. The semiconductor device according to claim 3, wherein the first layer includes a pair of impurity regions containing the impurity element.

5. The semiconductor device according to claim 1, wherein the semiconductor layer is formed using a material different from the material of the first layer, and wherein the semiconductor layer serves as a channel formation layer of the first transistor.

6. The semiconductor device according to claim 1, wherein the third conductive layer is in contact with the first conductive layer.

7. The semiconductor device according to claim 1, wherein the memory circuit further comprises a third insulating layer over the second insulating layer and the fourth conductive layer, and a fifth conductive layer over the third insulating layer,

wherein the fifth conductive layer is electrically connected to the first layer through a first opening penetrating the first to third insulating layers, and is electrically connected to the third conductive layer through a second opening penetrating the second and third insulating layers.

8. A semiconductor device comprising:

a plurality of memory cells arranged in I rows (I is a natural number of 2 or more) and J columns (J is a natural number), each the plurality of memory cells comprising;

a first transistor;

a second transistor;

a first layer serving as a channel formation layer of the second transistor;

a second layer formed using the same material and at the same time as the first layer, wherein the second layer is apart from the first layer and serves as a first gate of the first transistor;

a first insulating layer over the first layer and the second layer;

a first conductive layer overlapping with the first layer with the first insulating layer provided therebetween;

a semiconductor layer overlapping with the second layer with the first insulating layer provided therebetween;

a second conductive layer electrically connected to the semiconductor layer;

a third conductive layer electrically connected to the first conductive layer and the semiconductor layer;

a second insulating layer over the semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer overlapping with the semiconductor layer with the second insulating layer provided therebetween, the fourth conductive layer serving as a second gate of the first transistor,

wherein the first conductive layer is provided between the first insulating layer and the third conductive layer.

9. The semiconductor device according to claim 8, wherein the first layer and the second layer contain silicon and the semiconductor layer is an oxide semiconductor layer.

10. The semiconductor device according to claim 8, wherein the second layer contains an impurity element imparting conductivity.

11. The semiconductor device according to claim 10, wherein the first layer includes a pair of impurity regions containing the impurity element.

12. The semiconductor device according to claim 8, wherein the semiconductor layer is formed using a material different from the material of the first layer, and wherein the semiconductor layer serves as a channel formation layer of the first transistor.

13. The semiconductor device according to claim 8, wherein the third conductive layer is in contact with the first conductive layer.

14. The semiconductor device according to claim 8, wherein each the plurality of memory cells further comprises a third insulating layer over the second insulating layer and the fourth conductive layer, and a fifth conductive layer over the third insulating layer,

wherein the fifth conductive layer is electrically connected to the first layer through a first opening penetrating the first to third insulating layers, and is electrically connected to the third conductive layer through a second opening penetrating the second and third insulating layers.

15. A semiconductor device comprising:

a plurality of memory cells arranged in I rows (I is a natural number of 2 or more) and J columns (J is a natural number), each the plurality of memory cells comprising;

a first transistor;

a second transistor;

a first layer serving as a channel formation layer of the second transistor;

a second layer formed using the same material and at the same time as the first layer, wherein the second layer is apart from the first layer and serves as a first gate of the first transistor;

a first insulating layer over the first layer and the second layer;

a first conductive layer overlapping with the first layer with the first insulating layer provided therebetween;

a semiconductor layer overlapping with the second layer with the first insulating layer provided therebetween;

a second conductive layer electrically connected to the semiconductor layer;

a third conductive layer electrically connected to the first conductive layer and the semiconductor layer;

a second insulating layer over the semiconductor layer, the second conductive layer, and the third conductive layer; and

a fourth conductive layer overlapping with the semiconductor layer with the second insulating layer provided therebetween, the fourth conductive layer serving as a second gate of the first transistor,

wherein the first insulating layer serves as a gate insulating layer of the second transistor in each the plurality of memory cells, and

wherein the first conductive layer is provided between the first insulating layer and the third conductive layer.

16. The semiconductor device according to claim 15, wherein the first layer and the second layer contain silicon and the semiconductor layer is an oxide semiconductor layer.

17. The semiconductor device according to claim 15, wherein in the memory cells arranged in the same column, the second conductive layer of a first memory cell in a k-th row (k is a natural number of 2 or more and I or less) is electrically connected to the semiconductor layer of a second memory cell in a (k−

1)th row.

18. The semiconductor device according to claim 15, wherein the second layer contains an impurity element imparting conductivity.

19. The semiconductor device according to claim 18, wherein the first layer includes a pair of impurity regions containing the impurity element.

20. The semiconductor device according to claim 15, wherein the semiconductor layer is formed using a material different from the material of the first layer, and wherein the semiconductor layer serves as a channel formation layer of the first transistor.

21. The semiconductor device according to claim 15, wherein the third conductive layer is in contact with the first conductive layer.