Pixel structure and manufacturing method thereof
First Claim
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1. A pixel structure comprising:
- a substrate;
a scan line configured on the substrate;
a gate configured on the substrate and electrically connected to the scan line;
a gate insulating layer configured on the substrate and covering the gate and the scan line;
an active layer configured on the gate insulating layer and correspondingly located above the gate, the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region, wherein sheet resistance of the source region and sheet resistance the drain region are respectively lower than sheet resistance of the channel region;
a blocking layer configured on the channel region of the active layer and exposing the source region and the drain region;
a capacitor electrode configured on the gate insulating layer;
a source electrode located on the gate insulating layer and electrically connected to the source region of the active layer;
a drain electrode located on the gate insulating layer and electrically connected to the drain region of the active layer;
a data line configured on the gate insulating layer and electrically connected to the source electrode, an extension direction of the data line intersecting an extension line of the scan line;
a common line configured on the gate insulating layer and connected to the capacitor electrode, wherein an extension direction of the common line is substantially parallel to the extension direction of the data line;
a passivation layer configured on the gate insulating layer and covering the active layer, the blocking layer, the capacitor electrode, the source electrode, the drain electrode, the data line, and the common line, the passivation layer having a contact window exposing at least a portion of the drain electrode; and
a pixel electrode configured on the passivation layer, the pixel electrode being electrically connected to the drain electrode via the contact window.
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Abstract
A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.
14 Citations
21 Claims
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1. A pixel structure comprising:
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a substrate; a scan line configured on the substrate; a gate configured on the substrate and electrically connected to the scan line; a gate insulating layer configured on the substrate and covering the gate and the scan line; an active layer configured on the gate insulating layer and correspondingly located above the gate, the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region, wherein sheet resistance of the source region and sheet resistance the drain region are respectively lower than sheet resistance of the channel region; a blocking layer configured on the channel region of the active layer and exposing the source region and the drain region; a capacitor electrode configured on the gate insulating layer; a source electrode located on the gate insulating layer and electrically connected to the source region of the active layer; a drain electrode located on the gate insulating layer and electrically connected to the drain region of the active layer; a data line configured on the gate insulating layer and electrically connected to the source electrode, an extension direction of the data line intersecting an extension line of the scan line; a common line configured on the gate insulating layer and connected to the capacitor electrode, wherein an extension direction of the common line is substantially parallel to the extension direction of the data line; a passivation layer configured on the gate insulating layer and covering the active layer, the blocking layer, the capacitor electrode, the source electrode, the drain electrode, the data line, and the common line, the passivation layer having a contact window exposing at least a portion of the drain electrode; and a pixel electrode configured on the passivation layer, the pixel electrode being electrically connected to the drain electrode via the contact window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A manufacturing method of a pixel structure, comprising:
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providing a substrate; forming a first patterned metal layer on the substrate, the first patterned metal layer comprising a scan line and a gate, the gate being electrically connected to the scan line; forming a gate insulating layer on the substrate, the gate insulating layer covering the gate and the scan line; forming a patterned semiconductor layer on the gate insulating layer, the patterned semiconductor layer comprising an active layer and a capacitor electrode, wherein the active layer is correspondingly located above the gate, and the active layer comprises a source region, a drain region, and a channel region located between the source region and the drain region; forming a blocking layer on the channel region of the active layer, the blocking layer exposing the source region and the drain region; performing an annealing process on the source region and the drain region of the active layer and on the capacitor electrode with use of the blocking layer as a mask; forming a second patterned metal layer on the gate insulating layer, the second patterned metal layer comprising a data line, a common line, a source electrode, and a drain electrode, the source electrode being electrically connected to the source region of the active layer, the drain electrode being electrically connected to the drain region of the active layer, the data line being electrically connected to the source electrode, the data line intersecting the scan line, the common line being electrically connected to the capacitor electrode; forming a passivation layer on the gate insulating layer, the passivation layer covering the active layer, the blocking layer, the capacitor electrode, the source electrode, the drain electrode, the data line, and the common line; forming a contact window in the passivation layer, the contact window exposing at least a portion of the drain electrode; and forming a pixel electrode on the passivation layer, the pixel electrode being electrically connected to the drain electrode via the contact window. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification
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Current AssigneeAU Optronics Corporation
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Original AssigneeAU Optronics Corporation
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InventorsLin, Wu-Hsiung, Chen, Po-Hsueh, Chen, Shin-Shueh, Shen, Guang-Ren, Ye, Jia-Hong
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Primary Examiner(s)Cao, Phat X
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Assistant Examiner(s)Vieira, Diana C
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Application NumberUS13/089,298Publication NumberTime in Patent Office967 DaysField of Search257/59US Class Current257/59CPC Class CodesG02F 1/136213 Storage capacitors associat...G02F 2201/40 Arrangements for improving ...G02F 2202/10 semiconductorG02F 2203/01 transmissiveH01L 27/1225 with semiconductor material...H01L 27/1255 integrated with passive dev...H01L 29/41733 for thin film transistors w...H01L 29/7869 having a semiconductor body...
