Structure and fabrication process of super junction MOSFET

• US 8,604,541 B2
• Filed: 04/06/2012
• Issued: 12/10/2013
• Est. Priority Date: 04/08/2011
• Status: Expired due to Fees

• Current Assignee: Wuxi Versine Semiconductor Corp., Ltd.
• Original Assignee: Wuxi Versine Semiconductor Corp., Ltd.
• Inventors: Huang, Qin, Bai, Yuming, Gao, Yang
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US13/441,101
• Publication Number:
  US 20120256254A1
• Time in Patent Office: 613 Days
• Field of Search: 257/329, 257/378, 257/E29.256, 257/E29.262, 257/E21.41, 257/E21.418, 438/268
• US Class Current: 257/329
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.

Claims

1. A super junction metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:

a drain;

a first conductive substrate above the drain;

a source area above the first conductive substrate, from bottom to top, the source area including a first conductive drift area, a first conductive source area above the first conductive drift area, and a second conductive body area between the first conductive source area and the first conductive drift area;

a side-wall isolation structure being above the first conductive substrate and contacting with one side of the source area that is close to the first conductive source area, height of such isolation structure being lower than thickness of said source area such that the side-wall of the first conductive source and the second conductive body being not blocked by the side-wall isolation structure;

a gate being above the second conductive body area of the source area;

a surface isolation structure being above the gate and covering upper surfaces of the first conductive source area and the first conductive drift area;

a source electrode covering the surface isolation structure and it extending downward from one side of the source area that is close to the first conductive source area to reach above the side-wall isolation structure, and conductive with the first conductive source area and the second conductive body area.

2. The MOSFET of claim 1, characterized in that:

the gate area includes a gate isolation layer and a gate electrode layer above the gate isolation layer.

3. The MOSFET of claim 1, characterized in that:

there is another isolation layer above the gate electrode layer.

4. The MOSFET of claim 1, characterized in that:

the source area includes a field plate formed by an extension of a side wall of the side wall isolation structure.

5. The MOSFET of claim 1, characterized in that:

the source area includes the second conductive buffer layer which is located underneath the second conductive body area, contacts with the second conductive body area, the side-wall isolation structure and the first conductive drift area.

6. The MOSFET of claim 5, characterized in that:

the second conductive buffer layer is a lightly doped semiconductor material, said second conductive body is a heavily doped semiconductor material.

7. A fabrication process of super junction MOSFET of claim 1 comprising the following steps:

i) forming an epitaxial layer (EPI) above a semiconductor substrate and forming a gate area on the epitaxial layer;

ii) forming a surface isolation area around the gate area to cover both the gate area and partial upper surface of periphery of the gate area;

iii) forming a heavily doped first and second conductive areas inside the EPI on one side of the surface isolation area such that both the first and second conductive areas extend below the said surface isolation area and the second conductive area isolates the first conductive area from the rest of the EPI;

iv) using self aligned technology to etch along the surface isolation structure downward to etch off a part of the first conductive area and a part of the second conductive area which are not covered by the surface isolation structure, and forming a trench in the epitaxial layer;

v) applying heat treatment diffusion method to enlarge the first and second conductive areas such that the second conductive area is extended below the gate;

vi) filling dielectric materials in the trench, and using etch-back techniques to erase the excessive dielectric material to expose the side-wall of both the first and second conductive areas, remaining dielectric in the trench forms the side-wall isolation structure;

vii) making an upper electrode to make it cover the surface of the surface isolation structure, extend into the side wall isolation structure from the trench downward, and contact the side walls of the first and second conducive areas; and

viii) making the lower electrode underneath the semiconductor substrate.

8. The process according to claim 7, characterized in that the substrate specified in step i) is the first conductive substrate.

9. The process according to claim 7, characterized in that the substrate specified in step i) is the second conductive substrate.

10. The process according to claim 7, characterized in that the gate unit includes a gate dielectric layer and a gate layer above the gate dielectric layer as well as a nonconductive layer above the gate layer.

11. The process according to claim 7, characterized in that, the source formation specified in step vii) includes a field plate of the upper electrode formed by downward extension of side wall of the side-wall isolation structure.

12. A super junction metal-oxide-semiconductor field-effect transistor (MOSFET) comprising:

a drain;

a second conductive substrate above the drain;

a source area above the second conductive substrate, from bottom to top, the sources including a first conductive drift area, a first conductive emitting area above one side of the first conductive drift area, and the second conductive area between the first conductive emitting area and the first conductive drift area;

a side-wall isolation structure being above the second conductive substrate and contacting with one side of the source area that is close to the first conductive source area, height of such isolation structure being lower than thickness of said source area such that the side-wall of the first conductive emitting area and the second conductive body being not blocked by the side-wall isolation structure;

a gate being above the second conductive body area of the source area;

a surface isolation structure being above the gate and covering upper surfaces of the first conductive source area and the first conductive drift area;

a source electrode covering the surface isolation structure and it extending downward from one side of the source area that is close to the first conductive emitting area to reach in the side-wall isolation structure, and being conductive with the first conductive emitting area and the second conductive body area.

13. The MOSFET of claim 12, characterized in that:

the gate area includes a gate isolation layer and a gate electrode layer above the gate isolation layer.

14. The MOSFET of claim 13, characterized in that:

there is another isolation layer above the gate electrode layer.

15. The MOSFET of claim 12, characterized in that:

the source area includes a second conductive buffer layer which is located underneath the second conductive body area, and contacts with the second conductive body area, the side-wall isolation structure and the first conductive drift area.

16. The MOSFET of claim 15, characterized in that:

the second conductive buffer layer is a lightly doped semiconductor material, and said second conductive body is a heavily doped semiconductor material.

17. A fabrication process of super junction MOSFET of claim 12 comprising the following steps:

i) forming a first conductive epitaxial layer on a semiconductor substrate and forming a gate area on the epitaxial layer;

ii) forming a surface isolation structure around the gate area to cover both the gate area and a part of upper surface of the epitaxial around the gate area;

iii) forming of heavily doped first and second conductive areas inside the epitaxial layer on one side of the surface isolation area such that both the first and second conductive areas extend below the surface isolation structure, the second conductive area being the first conductive area and separating the first conductive area with the rest of the epitaxial layer;

iv) using self aligned technology to etch along the surface isolation structure downward to etch off a part of the first conductive area and a part of the second conductive area which are not covered by the surface isolation structure, and forming a trench in the epitaxial layer;

v) applying the tilt ion implantation method to form a second conductive lightly doped buffer layer underneath the second conductive area from the side wall of the trench;

vi) applying heat treatment diffusion method to enlarge the first and second conductive areas such that the second conductive area is extended below the gate

vii) using self alignment technology to etch off the excessive heavily doped second conductive material formed at the bottom of the trench due to the tilt ion implantation specified in step v) along the edge of the surface isolation structure downward;

viii) filling the trench with dielectric material and removing the extra dielectric material on upper part of the trench through etchback technique to expose the side-wall of the first and second conductive areas, the remaining dielectric material forming the side-wall isolation structure;

ix) making an upper electrode to make it cover the surface of the surface isolation structure, extend into the side wall isolation structure from the trench downward, and contact the side walls of the first and second conducive areas; and

x) making a lower electrode underneath the semiconductor substrate.

18. The fabrication process according to claim 17, characterized in that the substrate specified in step i) is the first conductive substrate.

19. The fabrication process according to claim 17, characterized in that the substrate specified in step i) is the second conductive substrate.

20. The fabrication process according to claim 17, characterized in that the gate unit includes a gate dielectric layer and a gate electrode layer above the gate dielectric layer, a nonconductive layer being above the gate electrode layer.

21. The fabrication process according to claim 17, characterized in that the upper electrode formation specified in step ix) includes forming a field plate part of the upper electrode by continuous extension downward of the side-wall isolation structure.

22. The fabrication process according to claim 17, characterized in that, prior to filing the trench in step viii), using isotropic etching to trim the surface isolation structure.