Semiconductor device assembly utilizing a DBC substrate

• US 8,604,611 B2
• Filed: 02/01/2013
• Issued: 12/10/2013
• Est. Priority Date: 12/21/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Hauenstein, Henning M.
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US13/756,963
• Publication Number:
  US 20130140684A1
• Time in Patent Office: 312 Days
• Field of Search: 257/723, 257/724, 257/704, 257/730, 257/731, 257/728, 257/699
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32503 comprising an intermetallic compound
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73153 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83139 Guiding structures on the body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/62 : Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

Claims

1. An assembly comprising:

first and second semiconductor devices, each of said first and second semiconductor devices comprising;

first and second conductive layers insulated from one another, said first conductive layer having a depression therein and a rim at least partially surrounding a bottom surface of said depression;

a semiconductor die situated in said depression and having an electrode electrically connected to said bottom surface of said depression;

a support substrate including a patterned conductive layer electrically connecting said first semiconductor device and said second semiconductor device, said first and second semiconductor devices each being electrically and mechanically connected to said patterned conductive layer.

2. The assembly of claim 1, wherein said patterned conductive layer is electrically connecting said rim of said first semiconductor device and said rim of said second semiconductor device.

3. The assembly of claim 1, wherein said support substrate further comprises a bottom conductive layer that is insulated from said patterned conductive layer.

4. The assembly of claim 1, a heat sink or plate mechanically and thermally connected to said second conductive layer of each of said first and second semiconductor devices.

5. The assembly of claim 1, comprising an EMI screening plate situated over said first and second semiconductor devices, said EMI screening plate electrically connected to said first and second semiconductor devices through said patterned conductive layer.

6. The assembly of claim 1, wherein another electrode of said first semiconductor device and another electrode of said second semiconductor device are each electrically and mechanically connected to said patterned conductive layer.

7. The assembly of claim 1, wherein said first and second conductive layers of each of said first and second semiconductor devices are on a common insulation layer.

8. The assembly of claim 1, comprising a first terminal electrically and mechanically connected to said second conductive layer of said first semiconductor device and a second terminal electrically and mechanically connected to said patterned conductive layer.

9. The assembly of claim 1, comprising an integrated circuit mounted atop and electrically connected to said first and second semiconductor devices.

10. The assembly of claim 1, wherein said support substrate is a direct bonded copper (DBC) substrate.

11. An assembly comprising:

a semiconductor device including first and second conductive layers insulated from one another, said first conductive layer having a depression therein and a rim at least partially surrounding a bottom surface of said depression;

a semiconductor die of said semiconductor device situated in said depression and having an electrode electrically connected to said bottom surface of said depression;

a support substrate including a patterned conductive layer electrically and mechanically connected to said semiconductor device;

an integrated circuit (IC) electrically and mechanically connected to said second conductive layer of said semiconductor device.

12. The assembly of claim 11, wherein said IC is electrically connected to said semiconductor die through wirebonds.

13. The assembly of claim 11 comprising wirebonds electrically connecting said IC to said semiconductor device through said second conductive layer.

14. The assembly of claim 11, wherein said IC is electrically connected to said second conductive layer through ball contacts.

15. The assembly of claim 11, wherein said IC is a prepackaged IC having IC terminals electrically and mechanically connected to said second conductive layer.

16. The assembly of claim 11, wherein said IC is a control IC of said semiconductor device.

17. The assembly of claim 11, wherein said IC is configured to measure a voltage drop across a shunt of said semiconductor device.

18. The assembly of claim 11 comprising an external interface terminal electrically and mechanically connected to said second conductive layer.

19. The assembly of claim 11, wherein said first and second conductive layers are on an insulation layer, a shunt in said insulation layer electrically connecting said first and second conductive layers.

20. The assembly of claim 11, wherein said rim of said semiconductor device is electrically and mechanically connected to said patterned conductive layer.