Vertical integrated circuit switches, design structure and methods of fabricating same

• US 8,604,898 B2
• Filed: 04/20/2009
• Issued: 12/10/2013
• Est. Priority Date: 04/20/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Felix P., Cooney, Edward C. III, McDevitt, Thomas L., Stamper, Anthony K.
• Primary Examiner(s): Rojas, Bernard
• Application Number:
  US12/426,561
• Publication Number:
  US 20100263998A1
• Time in Patent Office: 1,695 Days
• Field of Search: 296/22, 335/78, 200/181
• US Class Current: 335/78
• CPC Class Codes: H01H 59/0009 making use of micromechanics
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

Claims

1. A method of manufacturing a MEMS switch, comprising:

forming at least two vertically extending vias in a wafer;

filling the at least two vertically extending vias with a metal to form at least two vertically extending wires; and

opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

2. The method of claim 1, wherein:

the forming the at least two vertically extending vias includes etching four vertically extending vias from a top side of the wafer; and

the filling the at least two vertically extending vias with the metal includes filling the four vertically extending vias from the top side of the wafer to form four vertically extending wires; and

the opening includes etching the wafer from the bottom side such that two inner wires of the four vertically extending wires are moveable within the void in order to make contact with one another.

3. The method of claim 2, wherein:

the forming the at least two vertically extending vias further includes etching vias from the bottom side of the wafer;

the filling the at least two vertically extending vias with a metal further includes filling the bottom side vias with metal from the bottom side to form two wire extensions in contact with inner wires, respectively, of the four vertically extending wires; and

the opening includes etching the wafer from the bottom side such that the two wire extensions are moveable within the void in order to make contact with one another.

4. The method of claim 1, wherein:

the forming the at least two vertically extending vias includes;

etching four vertically extending vias from a top side of the wafer with inner of the four vertically extending vias being shallower than outer of the four vertically extending vias; and

etching two vias from the bottom side using a dual damascene process;

the filling the at least two vertically extending vias with the metal includes;

filling the four vertically extending vias from the top side of the wafer to form four vertically extending wires; and

filling the two vias from the bottom side of the wafer to form two bottom side wires which are in contact with inner wires of the four vertically extending wires, respectively; and

the opening includes etching the wafer from the bottom side such that the two bottom side wires are moveable within the void in order to make contact with one another.

5. The method of claim 1, wherein:

the forming at least two vertically extending vias in a wafer includes;

etching at least three vertically extending vias from a top side of the wafer, with an inner of the least three vertically extending vias being deeper than outer of the least three vertically extending vias; and

etching at least two vertically extending vias in the wafer from the bottom side;

the filling the at least two vertically extending vias with the metal includes;

filling the three vertically extending vias from the top side of the wafer with metal to form two partial wires and a middle longer wire;

filling the vertically extending vias in the wafer from the bottom side with metal to form bottom side wires, wherein the bottom side wires make contact with the two partial wires and are on sides of the middle longer wire; and

the opening includes etching the wafer from the bottom side such that a middle of the top side wires or the bottom side wires are moveable within the void.

6. The method of claim 1, wherein:

the forming at least two vertically extending vias in a wafer includes;

etching three vertically extending vias in the wafer from a top side of the wafer, wherein a middle of the three vertically extending vias is deeper than outer of the three vertically extending vias; and

etching one via in the wafer from the bottom side of the wafer which is off set from the middle of the three vertically extending vias;

the filling the at least two vertically extending vias with a metal includes filling the three vertically extending vias and the bottom side via with the metal to form wires; and

the opening includes etching the wafer from the bottom side such that a middle of the three vertically extending wires is freely moveable within the void to make contact with the wire formed from the bottom side of the wafer.

7. The method of claim 1, wherein:

the forming at least two vertically extending vias in a wafer includes;

forming two vertically extending vias in the wafer from a top side of the wafer; and

forming one via in the wafer from a bottom side of the wafer;

the filling the at least two vertically extending vias with a metal includes filling the two vertically extending vias and the bottom side via with the metal to form wires; and

the opening includes etching the wafer from the bottom side such that one of the two vertically extending wires is freely moveable within the void and makes contact with the wire formed from the bottom side of the wafer.

8. The method of claim 1, wherein

the forming at least two vertically extending vias in a wafer includes:

forming one vertically extending vias in the wafer from a top side of the wafer; and

forming one via in the wafer from a bottom side of the wafer;

the filling the at least two vertically extending vias with a metal includes filling the one vertically extending via and the bottom side via with the metal to form wires; and

the opening includes etching the wafer from the bottom side such that the vertically extending wire is moveable within the void.

9. The method of claim 1, further comprising hermetically sealing the void.

10. The method of claim 1, further comprising applying a voltage to at least one of two vertically extending wires in order to move the other of the two vertically extending wires.

11. The method of claim 1, further comprising:

grinding the bottom side of the wafer to expose a portion of at least one of the filling the at least two vertically extending wires; and

protecting portions of the bottom side of the wafer prior to forming the void in order to have at least one of the at least two vertically extending wires fixed to the wafer.

12. A method of manufacturing a MEMS switch comprising:

etching at least three vias from a top side of a wafer;

filling the vias with a metal to form vertically arranged top side wires;

depositing a dielectric material on the bottom side of the wafer;

etching the dielectric material to form an opening therein, wherein remaining portions of the dielectric material protect edges of the wafer; and

etching a bottom side of the wafer through the opening in the dielectric material to form a void which exposes at least one of the vertically arranged top side wires.

13. The method of claim of claim 12, wherein the at least three vias are four vias formed into four vertically arranged top side wires, and further comprising grinding the bottom side of the wafer to expose a portion of two inner of the four vertically arranged top side wires prior to the etching the bottom side, wherein the void accommodates the two inner wires which are moveable therein.

14. The method of claim 13, further comprising:

etching the bottom side of the wafer to form two vias which align with the two inner of the four vertically arranged top side wires; and

filling the two bottom side vias with metal to form metal wire extensions extending from the inner of the four vertically arranged top side wires, toward one another, wherein the metal wire extensions are moveable within the void.

15. The method of claim of claim 12, wherein the at least three vias are four vias formed into four vertically arranged top side wires and two vias formed into two vertically arranged bottom side wires, and further comprising grinding the bottom side of the wafer to expose a portion of two outer of the four vertically arranged top side wires prior to the etching the bottom side, wherein the void accommodates the bottom side wires which are moveable therein.

16. A design structure comprising instructions tangibly embodied in a non-transitory computer readable storage medium for designing, manufacturing, or testing an integrated circuit, the instructions when processed on a data processing system generate a functional representation of the integrated, the design structure comprising:

at least two vertically extending metal wires formed in a wafer; and

a void formed in the wafer which accommodates at least one of the at least two vertically extending metal wires,

wherein the at least one of the at least two vertically extending metal wires is moveable within the void upon an application of a voltage.

17. The design structure of claim 16, wherein the design structure comprises a netlist.

18. The design structure of claim 16, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

19. The design structure of claim 16, wherein the design structure resides in a programmable gate array.