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Timing controller, liquid crystal display having the same, and method of driving liquid crystal display

  • US 8,605,026 B2
  • Filed: 06/23/2008
  • Issued: 12/10/2013
  • Est. Priority Date: 10/18/2007
  • Status: Expired due to Fees
First Claim
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1. A liquid crystal display comprising:

  • a plurality of light-emitting blocks whose respective luminances are individually controllable in response to supplied and respective luminance control signals;

    a plurality of display blocks each having two or more pixels and each corresponding to a respective light-emitting block;

    a first timing controller structured and coupled for receiving image signals in synchronization with a supplied first clock signal, the received image signals corresponding to pixels of the display blocks, and for generating and outputting a data control signal corresponding to the image signals and representative image signals that are representative of luminances of respective ones of the display blocks where the representative image signals are output in synchronization with a second clock signal, the frequency of the second clock signal being lower than the frequency of the first clock signal;

    luminance control circuitry structured and coupled for controlling luminance of the light-emitting blocks of the liquid crystal display in response to the generated representative image signals;

    a second timing controller for outputting backlight data signals corresponding to the representative image signals;

    a plurality of backlight drivers for controlling luminance of light-emitting blocks in response to the backlight data signals; and

    a data driver outputting data signals to the plurality of display blocks in response to the data control signal;

    wherein the first timing controller comprises;

    a memory;

    a representative-value generator for receiving the image signals, generating the representative image signals, and writing the representative image signals to the memory in synchronization with the first clock signal; and

    a serializer for reading the representative image signals from the memory in synchronization with the second clock signal, and serially outputting the read representative image signals to the second timing controller.

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