Semiconductor memory device

• US 8,605,477 B2
• Filed: 04/25/2011
• Issued: 12/10/2013
• Est. Priority Date: 04/27/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Lam, David
• Application Number:
  US13/093,018
• Publication Number:
  US 20110260158A1
• Time in Patent Office: 960 Days
• Field of Search: 365/63, 365/51, 365/149, 365/72
• US Class Current: 365/63
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

To provide a semiconductor memory device storing data, in which a transistor whose leakage current between a source/drain in off state is small is used as a writing transistor. In a matrix of a memory unit formed of two memory cells, in each of which a drain of a writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor, a gate of the writing transistor, and the other electrode of the capacitor in a first memory cell are connected to a first word line, and a second word line, respectively. In a second memory cell, a gate of the writing transistor, and the other electrode of the capacitor are connected to the second word line, and the first word line, respectively. Further, to increase the degree of integration, gates of the reading transistors of memory cells are disposed in a staggered configuration.

Claims

1. A semiconductor memory device comprising a first wiring, a second wiring, a third wiring, a fourth wiring, and a memory unit including a first memory cell and a second memory cell, which are arranged in a matrix,

wherein the first wiring is parallel to the second wiring,

wherein the third wiring is parallel to the fourth wiring,

wherein the first wiring is orthogonal to the third wiring,

wherein the first memory cell includes a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell includes a third transistor, a fourth transistor, and a second capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a gate of the first transistor and the other electrode of the second capacitor are connected to the first wiring,

wherein a gate of the third transistor and the other electrode of the first capacitor are connected to the second wiring,

wherein a source of the first transistor, a source of the second transistor, and a drain of the fourth transistor are connected to the third wiring, and

wherein a source of the third transistor, a source of the fourth transistor, and a drain of the second transistor are connected to the fourth wiring.

2. The semiconductor memory device according to claim 1, wherein the first transistor has a different conductivity type from the second transistor.

3. The semiconductor memory device according to claim 1, wherein a conductivity type of the first transistor is an n-channel type.

4. The semiconductor memory device according to claim 1, wherein a conductivity type of the second transistor is a p-channel type.

5. The semiconductor memory device according to claim 1, wherein the third transistor has a different conductivity type from the fourth transistor.

6. The semiconductor memory device according to claim 1, wherein a conductivity type of the third transistor is an n-channel type.

7. The semiconductor memory device according to claim 1, wherein a conductivity type of the fourth transistor is a p-channel type.

8. The semiconductor memory device according to claim 1, wherein at least one of the first transistor and the third transistor includes a channel including a semiconductor having a bandgap of 2.5 eV or larger.

9. The semiconductor memory device according to claim 8, wherein the semiconductor is an oxide semiconductor.

10. The semiconductor memory device according to claim 9, wherein the oxide semiconductor comprises at least one of gallium, indium, and zinc.

11. The semiconductor memory device according to claim 1, further comprising a device which supplies the same signal to the third wiring and the fourth wiring when data is written.

12. A semiconductor memory device comprising a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, which are arranged in a matrix,

wherein the first wiring is parallel to the second wiring,

wherein the third wiring, the fourth wiring, and the fifth wiring are parallel to each other,

wherein the first wiring is orthogonal to the third wiring,

wherein the first memory cell includes a first transistor, a second transistor, and a first capacitor,

wherein the second memory cell includes a third transistor, a fourth transistor, and a second capacitor,

wherein the third memory cell includes a fifth transistor, a sixth transistor, and a third capacitor,

wherein the fourth memory cell includes a seventh transistor, an eighth transistor, and a fourth capacitor,

wherein a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a drain of the third transistor is connected to a gate of the fourth transistor and one electrode of the second capacitor,

wherein a drain of the fifth transistor is connected to a gate of the sixth transistor and one electrode of the third capacitor,

wherein a drain of the seventh transistor is connected to a gate of the eighth transistor and one electrode of the fourth capacitor,

wherein a gate of the first transistor, the other electrode of the second capacitor, a gate of the fifth transistor, and the other electrode of the fourth capacitor are connected to the first wiring,

wherein a gate of the third transistor, the other electrode of the first capacitor, a gate of the seventh transistor, and the other electrode of the third capacitor are connected to the second wiring,

wherein a source of the first transistor, a source of the second transistor, and a drain of the fourth transistor are connected to the third wiring,

wherein a source of the third transistor, a source of the fourth transistor, a drain of the second transistor, a source of the fifth transistor, a source of the sixth transistor, and a drain of the eighth transistor are connected to the fourth wiring, and

wherein a source of the seventh transistor, a source of the eighth transistor, and a drain of the sixth transistor are connected to the fifth wiring.

13. The semiconductor memory device according to claim 12, wherein the first transistor and the third transistor have the same conductivity type.

14. The semiconductor memory device according to claim 12, wherein the second transistor and the fourth transistor have the same conductivity type.

15. The semiconductor memory device according to claim 12, wherein the first transistor has a different conductivity type from the second transistor.

16. The semiconductor memory device according to claim 12, wherein a conductivity type of the first transistor and the third transistor is an n-channel type.

17. The semiconductor memory device according to claim 12, wherein a conductivity type of the second transistor and the fourth transistor is a p-channel type.

18. The semiconductor memory device according to claim 12, wherein at least one of the first transistor, the third transistor, the fifth transistor, and the seventh transistor includes a channel including a semiconductor having a bandgap of 2.5 eV or larger.

19. The semiconductor memory device according to claim 18, wherein the semiconductor is an oxide semiconductor.

20. The semiconductor memory device according to claim 19, wherein the oxide semiconductor comprises at least one of gallium, indium, and zinc.

21. The semiconductor memory device according to claim 12, further comprising a device which supplies the same signal to the third wiring and the fourth wiring when data is written.

22. A semiconductor memory device comprising:

a first electrode, a second electrode, a third electrode, and a fourth electrode over a substrate,

a first connection electrode between the first electrode and the second electrode,

a second connection electrode between the third electrode and the fourth electrode,

a first semiconductor, a second semiconductor, a third semiconductor, and a fourth semiconductor over the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively,

a first wiring over the first electrode, the third electrode, the first semiconductor and the third semiconductor, and

a second wiring over the second electrode, the fourth electrode, the second semiconductor and the fourth semiconductor,

wherein the first electrode, the second electrode, and the first connection electrode are arranged in a line in a first direction,

wherein the third electrode, the fourth electrode, and the second connection electrode are arranged in a line in a second direction,

wherein the first wiring is parallel to the second wiring in a third direction, and

wherein the first direction and the second direction are orthogonal to the third direction.

23. The semiconductor memory device according to claim 22, wherein at least one of the first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor includes a channel including a semiconductor having a bandgap of 2.5 eV or larger.

24. The semiconductor memory device according to claim 22, wherein at least one of the first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor is an oxide semiconductor.

25. The semiconductor memory device according to claim 24, wherein the oxide semiconductor comprises at least one of gallium, indium, and zinc.

26. The semiconductor memory device according to claim 22, wherein the substrate is a single crystal silicon substrate.

27. A semiconductor memory device comprising:

a first electrode, a second electrode, a third electrode, and a fourth electrode over a substrate,

a connection electrode between the first electrode, the third electrode and the second electrode, the fourth electrode,

a first semiconductor over the first electrode,

a second semiconductor over the second electrode, the third electrode, and the connection electrode,

a third semiconductor over the fourth electrode, and

a first wiring, a second wiring, a third wiring, and a fourth wiring over the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively, and over the first semiconductor, the second semiconductor, and the third semiconductor,

wherein the first electrode and the third electrode are arranged in a line in a first direction,

wherein the second electrode and the fourth electrode are arranged in a line in a second direction,

wherein the first direction is parallel to the second direction,

wherein the first wiring, the second wiring, the third wiring, and the fourth wiring are parallel to each other in a third direction, and

wherein the first direction and the second direction are orthogonal to the third direction.

28. The semiconductor memory device according to claim 27, wherein at least one of the first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor includes a channel including a semiconductor having a bandgap of 2.5 eV or larger.

29. The semiconductor memory device according to claim 27, wherein at least one of the first semiconductor, the second semiconductor, the third semiconductor, and the fourth semiconductor is an oxide semiconductor.

30. The semiconductor memory device according to claim 29, wherein the oxide semiconductor comprises at least one of gallium, indium, and zinc.

31. The semiconductor memory device according to claim 27, wherein the substrate is a single crystal silicon substrate.