Non-volatile semiconductor storage device having control circuit to control voltages to select transistor for erase operation

• US 8,605,508 B2
• Filed: 05/04/2012
• Issued: 12/10/2013
• Est. Priority Date: 01/08/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Itagaki, Kiyotaro, Iwata, Yoshihisa, Tanaka, Hiroyasu, Kidoh, Masaru, Kito, Masaru, Katsumata, Ryota, Aochi, Hideaki, Nitayama, Akihiro, Maeda, Takashi, Hishida, Tomoo
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/463,889
• Publication Number:
  US 20120218821A1
• Time in Patent Office: 585 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.18, 365/185.29
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Claims

1. A non-volatile semiconductor storage device comprising:

a first memory string including a plurality of memory cells connected in series;

a first selection transistor having one end electrically connected to one end of the first memory string;

a first wiring electrically connected to the other end of the first selection transistor;

a second wiring electrically connected to a gate of the first selection transistor; and

a control circuit configured to perform erase operation, the control circuit being configured to boost the first wiring to a first voltage and to boost the second wiring to a second voltage in the erase operation, the first voltage being higher than the second voltage, and then the control circuit being configured to start to boost the first wiring from the first voltage to an erase voltage.

2. The non-volatile semiconductor storage device according to claim 1, wherein the control circuit comprises:

a first voltage generation circuit configured to supply the first voltage wiring; and

a second voltage generation circuit configured to supply the second voltage, the second voltage being lower than the first voltage, the second voltage delaying the first voltage.

3. The non-volatile semiconductor storage device according to claim 1, further comprising:

a plurality of memory blocks each including the first memory string;

a second selection transistor having one end connected to the other end of the first memory string; and

a third wiring electrically connected to the other end of the second selection transistor,

wherein the control circuit is configured to control a first gate voltage of the first selection transistor in a selected memory block and a second gate voltage of the second selection transistor in a selected memory block, the first gate voltage and the second gate voltage being different from the voltage of the third wiring in a first period of the erase operation.

4. The non-volatile semiconductor storage device according to claim 1, wherein the first wiring is a source line, and the second wiring is a source-side selection gate line.

5. The non-volatile semiconductor storage device according to claim 1, further comprising:

a plurality of memory blocks each including the first memory string;

a second selection transistor having one end connected to the other end of the first memory string;

a third wiring electrically connected to the other end of the second selection transistor; and

a fourth wiring electrically connected to a gate of the memory cell,

wherein the control circuit is configured to control a voltage of the fourth wiring in a selected memory block, the voltage of the fourth wiring being different from the voltage of the third wiring in a first period of the erase operation.

6. The non-volatile semiconductor storage device according to claim 1, further comprising:

a plurality of memory blocks each including the first memory string;

a second selection transistor having one end connected to the other end of the first memory string; and

a third wiring electrically connected to the other end of the second selection transistor,

wherein the control circuit is configured to control a first gate voltage of the first selection transistor in an unselected memory block and a second gate voltage of the second selection transistor in an unselected memory block, the first gate voltage and the second gate voltage being different from the voltage of the third wiring in a first period of the erase operation.

7. The non-volatile semiconductor storage device according to claim 1, wherein a difference between the first voltage and the second voltage is substantially same as a threshold voltage of the first selection transistor.

8. The non-volatile semiconductor storage device according to claim 3, wherein a difference between the first voltage and the second voltage is substantially same as a threshold voltage of the first selection transistor.

9. The non-volatile semiconductor storage device according to claim 5, wherein a difference between the first voltage and the second voltage is substantially same as a threshold voltage of the first selection transistor.

10. The non-volatile semiconductor storage device according to claim 6, wherein a difference between the first voltage and the second voltage is substantially same as a threshold voltage of the first selection transistor.

11. The non-volatile semiconductor storage device according to claim 1, further comprising

a plurality of transfer transistors each having one end connected to a gate of the memory cell, the transfer transistors each having a gate, a voltage provided to the gate being changed.

12. The non-volatile semiconductor storage device according to claim 3, further comprising

a plurality of transfer transistors each having one end connected to a gate of the memory cell, the transfer transistors each having a gate, a voltage provided to the gate being changed.

13. The non-volatile semiconductor storage device according to claim 5, further comprising

a plurality of transfer transistors each having one end connected to a gate of the memory cell, the transfer transistors each having a gate, a voltage provided to the gate being changed.

14. The non-volatile semiconductor storage device according to claim 1, further comprising a second memory string serially connected to the first memory string,

wherein each of the first and second memory strings includes first to fourth memory cells,

the second memory cell is provided above the first memory cell,

the third memory cell is provided above the second memory cell, and

the fourth memory cell is provided above the third memory cell.

15. The non-volatile semiconductor storage device according to claim 3, further comprising a second memory string serially connected to the first memory string,

wherein each of the first and second memory strings includes first to fourth memory cells,

the second memory cell is provided above the first memory cell,

the third memory cell is provided above the second memory cell, and

the fourth memory cell is provided above the third memory cell.

16. The non-volatile semiconductor storage device according to claim 5, further comprising a second memory string serially connected to the first memory string,

wherein each of the first and second memory strings includes first to fourth memory cells,

the second memory cell is provided above the first memory cell,

the third memory cell is provided above the second memory cell, and

the fourth memory cell is provided above the third memory cell.