Tracking capacitive loads

• US 8,605,523 B2
• Filed: 02/17/2012
• Issued: 12/10/2013
• Est. Priority Date: 02/17/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tao, Derek C., Kim, Young Seog, Hsu, Kuoyuan (Peter), Wang, Bing, Lum, Annie-Li-Keow
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US13/399,877
• Publication Number:
  US 20130215693A1
• Time in Patent Office: 662 Days
• Field of Search: 365/194, 365/149
• US Class Current: 365/194
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.

Claims

1. A method comprising:

determining a time delay to cover a timing of a memory cell in a memory macro having a tracking circuit;

based on the time delay, determining a capacitance corresponding to the time delay; and

utilizing a capacitor having the determined capacitance,

wherein

the determined capacitance of the capacitor affects a transition of a signal of a first data line of a tracking cell of the tracking circuit; and

the transition of the signal of the of the first data line causes a first transition of a signal of a second data line of the memory cell.

2. The method of claim 1, wherein

determining the time delay is based on a plurality of current values of currents sunk by a corresponding plurality of memory cells of the memory macro.

3. The method of claim 2, wherein

determining the time delay is based on a one-sigma, a two-sigma, a three-sigma, a four-sigma, a five sigma, or a six-sigma value of the plurality of current values.

4. The method of claim 1, wherein

the capacitor is selected from a group consisting of a pair of conductive lines, a metal-oxide semiconductor capacitor, a diffusion capacitor, and a poly capacitor.

5. The method of claim 4, wherein

a conductive line of the pair of conductive lines is selected from a group consisting of a first conductive line, a reference voltage conductive line, and an operational voltage conductive line.

6. The method of claim 4, wherein

a conductive line of the pair of conductive lines is from an interface cell area between a memory circuit area and a logic circuit area of the memory macro.

7. The method of claim 1, wherein the capacitor is formed by a metal-oxide semiconductor transistor manufactured by a memory process or a logic process.

8. The method of claim 1, wherein

a first transition of a clock signal causes a first transition of a signal of a third data line;

the first transition of the signal of the third data line causes the first transition of the signal of the first data line;

the first transition of the signal of the first data line causes a second transition of the signal of the third data line;

the second transition of the signal of the third data line causes the first transition of the signal of the second data line; and

the first transition of the clock signal causes a second transition of the signal of the second data line.

9. The method of claim 8, wherein

the first transition of the clock signal is rising;

the first transition of the signal of the third data line is rising;

the first transition of the signal of the first data line is falling;

the second transition of the signal of the third data line is falling;

the first transition of the signal of the second data line is rising; and

the second transition of the signal of the second data line is falling.

10. A tracking circuit comprising:

a first circuit;

a first tracking cell;

a first data line coupled to the first circuit and the first tracking cell;

a second data line coupled to the first circuit; and

a capacitive device coupled to the first data line,

wherein

the capacitive device is configured to have a capacitance that causes a predetermined time delay in a signal transition of the first data line,

the signal transition of the first data line is configured to generate a signal transition of the second data line, and

the signal transition of the second data line is configured to generate a signal transition of a memory cell.

11. The tracking circuit of claim 10, wherein

the capacitive device is selected from a group consisting of a pair of conductive lines, a metal-oxide semiconductor capacitor, a diffusion capacitor, and a poly capacitor.

12. The tracking circuit of claim 11, wherein

a conductive line of the pair of conductive lines is selected from the group consisting of a first conductive line, a reference voltage line, and an operational voltage line.

13. The tracking circuit of claim 11, wherein a conductive line of the pair of conductive lines is from an interface cell area located between a memory cell area and a logic cell area of a memory macro having the tracking circuit.

14. The tracking circuit of claim 10, wherein

the capacitive device includes a first capacitor and a second capacitor;

and

the first capacitor is formed by a first conductive line and a first reference voltage line, and the second capacitor is formed by the first conductive line and a second reference voltage line;

or

the first capacitor is formed by a second conductive line and a first operational voltage line, and the second capacitor is formed by the second conductive line and a second operational voltage line;

or

the first capacitor is formed by a third conductive line and a third reference voltage line, and the second capacitor is formed by the third conductive line and a third operational voltage line.

15. The tracking circuit of claim 10, further comprising at least one third data line coupled to the first data line, each of a data line of the at least one third data line coupled to a corresponding tracking cell.

16. A method comprising:

generating a first transition of a signal of a first data line of a tracking cell coupled to a second data line of a tracking circuit;

generating a first transition of a signal of the second data line based on the first transition of the signal of the first data line;

generating a first transition of a signal of a third data line based on the first transition of the signal of the second data line and a first circuit configured to receive the second data line and provide the third data line; and

generating a first transition of a signal of a fourth data line used in accessing a memory cell,

wherein

the signal of the second data line is affected by a capacitive load of at least one capacitor selected from the group consisting of a conductive line capacitor, a metal-oxide semiconductor capacitor, a diffusion capacitor, and a poly capacitor.

17. The method of claim 16, wherein

the conductive line capacitor includes a pair of conductive lines, a conductive line of the pair of conductive lines is selected from a group consisting of a first conductive line, a reference voltage line, and an operational voltage line.

18. The method of claim 16, wherein

the conductive line capacitor includes a pair of conductive lines, a conductive line of the pair of conductive lines is from an interface cell area located between a memory cell area and a logic circuit area of a memory macro having the tracking circuit.

19. The method of claim 16, wherein

the at least one capacitor includes a first conductive line capacitor and a second conductive line capacitor;

the first conductive line capacitor is formed by a first conductive line and a first reference voltage line, and the second conductive line capacitor is formed by the first conductive line and a second reference voltage line;

or

the first conductive line capacitor is formed by a second conductive line and a first operational voltage line, and the second conductive line capacitor is formed by the second conductive line and a second operational voltage line;

or

the first conductive line capacitor is formed by a third conductive line and a third reference voltage line, and the second conductive line capacitor is formed by the third conductive line and a third operational voltage line.

20. The method of claim 16, wherein the metal-oxide semiconductor capacitor is manufactured by either a memory process or a logic process.