Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

• US 8,605,534 B2
• Filed: 09/09/2010
• Issued: 12/10/2013
• Est. Priority Date: 09/09/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Lee, Winston, Kim, Ha Soo
• Primary Examiner(s): King, Douglas
• Application Number:
  US12/878,703
• Publication Number:
  US 20110058439A1
• Time in Patent Office: 1,188 Days
• Field of Search: 365/226, 365/227, 365/229, 365/230.06
• US Class Current: 365/227
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

Claims

1. A dual power supply memory, comprising:

peripheral circuitry operating at a first voltage;

a memory array operating at a second voltage;

translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage from a power rail providing the second voltage;

a bias source coupled serially between a power plane in the memory array and an external power potential; and

a switch coupled to the power plane and the external power potential, the switch configured to bypass the bias source when the memory is in a standard operating mode.

2. The memory of claim 1, wherein the second voltage is greater than the first voltage.

3. The memory of claim 2, wherein the second voltage is greater than the first voltage plus a threshold voltage of one or more transistors in the translation circuitry, the one or more transistors being in a leakage path from the power rail providing the second voltage to the peripheral circuitry.

4. The memory of claim 3, wherein the translation circuitry comprises:

a logic gate configured to select either the second voltage or an output from the peripheral circuitry in response to a control or address signal, and

a buffer configured to receive an output from the logic gate and provide a row selection signal to a word line in the memory array, the row selection signal having the second voltage when selecting the word line.

5. The memory of claim 4, wherein when the control or address signal is active, the control or address signal has the first voltage, and the logic gate comprises:

a first transistor configured to select the second voltage when the control or address signal is inactive; and

a second transistor configured to select the output from the peripheral circuitry when the control or address signal is active.

6. The memory of claim 5, wherein

the peripheral circuitry comprises an address decoder, and the output from the peripheral circuitry comprises a word line selection signal;

and

a current leakage path through at least the first transistor exists when the word line selection signal is active.

7. The memory of claim 5, wherein a maximum ratio of the second voltage to the first voltage is determined by a ratio of the second transistor to the first transistor.

8. The memory of claim 1, wherein the output to the memory array is configured to enable a read and/or write operation in the memory array.

9. The memory of claim 1, further comprising a noise reduction switch coupled between a first power rail in the peripheral circuitry and a second power rail in the memory array, the noise reduction switch configured to reduce noise on the first and second power rails, wherein the second voltage is about equal to the first voltage.

10. The memory of claim 1, further comprising:

a bias source coupled serially between a ground plane in the memory array and an external ground potential, the bias source being configured to raise a voltage of a ground plane in the memory array when the memory is in power-down or leakage reduction mode; and

a leakage reduction switch coupled serially between the ground plane in the memory array and the external ground potential, the leakage reduction switch configured to selectively bypass the bias source.

11. The memory of claim 10, further comprising:

a memory controller configured to control the leakage reduction switch; and

a switch configured to disconnect a power supply providing the first voltage from a power rail in the peripheral circuitry.

12. The memory of claim 1, wherein the peripheral circuitry comprises one or more registers storing a first value of read and/or write timing control signals, one or more non-volatile storage elements storing a second value of the read and/or write timing control signals, and a multiplexer configured to select either the first value from the one or more registers or a second value from the one or more non-volatile storage elements.

13. The memory of claim 1, wherein the peripheral circuitry comprises precharge circuitry configured to precharge bitlines in the memory array to the first voltage.

14. The memory of claim 1, wherein the translation circuitry includes a power-down switch configured to turn off row decoders in the memory array, connect wordlines in the memory array to a ground potential, turn off bitline precharge devices in the peripheral circuitry, and/or isolate bitlines in the memory array from the peripheral circuitry.

15. A memory, comprising:

peripheral circuitry receiving a first voltage from a peripheral power rail;

a memory array receiving the first voltage or a second voltage from a memory array power rail;

a bias source coupled serially between a ground plane in the memory array and an external ground potential; and

a leakage reduction switch coupled serially between the ground plane in the memory array and the external ground potential, the leakage reduction switch configured to selectively bypass the bias source.

16. The memory of claim 15, further comprising:

a power supply configured to provide the first voltage; and

a power-down switch configured to selectively disconnect the peripheral power rail and the power supply.

17. The memory of claim 15, wherein the memory array receives the first voltage from the memory array power rail, and the memory further comprises a noise reduction switch coupled between the memory array power rail and the peripheral power rail, the noise reduction switch configured to electrically connect and disconnect the peripheral power rail and the memory array power rail.

18. The memory of claim 15, wherein the memory array receives the second voltage from the memory array power rail, and the memory further comprises a voltage regulator configured to receive the first voltage and provide the second voltage to the memory array power rail.

19. The memory of claim 15, further comprising:

a bias source coupled serially between a power plane in the memory array and an external power potential; and

a switch coupled to the power plane and the external power potential, the switch configured to bypass the bias source when the memory is in the standard operating mode.

20. A method for reducing power consumption in a memory, the method comprising:

operating peripheral circuitry at a first voltage, wherein the peripheral circuitry is coupled to a first power rail;

operating a memory array at the first voltage or a second voltage, wherein the second voltage is different from the first voltage, and the memory array is coupled to a second power rail;

coupling the first and second power rails when the memory array operates at the first voltage, otherwise not coupling the first and second power rails; and

reducing leakage in the memory array during a power down or leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail;

wherein reducing leakage in the memory array comprises applying a positive bias to the ground plane of the memory array.

21. The method of claim 20, wherein the first power rail receives the first voltage from a first power supply, the second power rail receives the second voltage from a second power supply, and the method further comprises disconnecting the first power rail from the first power supply during the power down or leakage reduction mode.

22. The method of claim 20, wherein the first power rail receives the first voltage from a variable power supply, the second power rail receives the first or second voltage from the variable power supply, and reducing leakage in the memory array comprises reducing the voltage from the variable power supply during the power down or leakage reduction mode.

23. The method of claim 20, wherein reducing leakage in the memory array during the power down or leakage reduction mode comprises applying an internal or external control signal to one or more switches configured to reduce the voltage differential between the ground plane in the memory array and the second power rail.

24. The method of claim 20, further comprising precharging bitlines in the memory array to the first voltage during a standard operating operational mode.