Methods and apparatus for in-pixel filtering in focal plane arrays

• US 8,605,853 B2
• Filed: 09/08/2011
• Issued: 12/10/2013
• Est. Priority Date: 07/01/2011
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Schultz, Kenneth I., Tyrrell, Brian, Kelly, Michael W., Colonero, Curtis, Candell, Lawrence M., Mooney, Daniel
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US13/228,367
• Publication Number:
  US 20130003911A1
• Time in Patent Office: 824 Days
• Field of Search: None
• US Class Current: 377/118
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 23/548 Reversible counters
• CPC Class Codes: H03M 1/001 Analogue/digital/analogue conversion
• CPC Class Codes: H03M 1/004 Reconfigurable analogue/digital or digital/analogue converters H03M1/02 takes precedence
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

Claims

1. An apparatus for counting pulses in a series of pulses representing an analog signal, the apparatus comprising:

an integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises;

a plurality of counters operably configured to count at least one pulse in the series of pulses representing the analog signal, wherein at least one counter in the plurality of counters is configured to be switched from a first operating mode to a second operating mode independently of operating modes of the other counters in the plurality of counters;

a converter to generate the series of pulses representing the analog signal; and

at least one multiplexer operably coupled to the converter and the at least one counter in the plurality of counters to provide the series of pulses to each counter in the plurality of counters and to switch the at least one counter in the plurality of counters from a count mode to a shift register mode.

2. The apparatus of claim 1, wherein the first operating mode is a count-up mode and the second operating mode is a count-down mode.

3. The apparatus of claim 1, wherein the integrated circuit is further configured to vary an integration period of the at least one counter in the plurality of counters.

4. The apparatus of claim 1, wherein the integrated circuit is further configured to vary a magnitude of the analog signal represented by a least significant bit of the at least one counter in the plurality of counters.

5. The apparatus of claim 1, wherein the at least one counter is a first counter having an output coupled to an input of a second counter in the plurality of counters, and wherein the first counter is configured to shift data to the second counter in response to a shift signal.

6. The apparatus of claim 1, wherein the converter includes a current-to-frequency converter.

7. The apparatus of claim 1, wherein the at least one unit cell further comprises:

a gating circuit operably coupled to the at least one counter to prevent the at least one counter from transferring data when the at least one counter is in the count mode.

8. An apparatus for counting pulses in a series of pulses representing an analog signal, the apparatus comprising:

an integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises;

a plurality of counters operably configured to count at least one pulse in the series of pulses representing the analog signal, the plurality of counters comprising a first counter configured to be switched from a first operating mode to a second operating mode independently of an operating mode of a second counter in the plurality of counters; and

a clock, operably coupled to the first counter and to the second counter, to supply an in-phase clock signal to the first counter and a quadrature clock signal to the second counter,

wherein the first and second counters are configured to switch between count-up and count-down modes in response to the in-phase and quadrature clock signals, respectively.

9. The apparatus of claim 8, wherein the integrated circuit is further configured to vary an integration period of at least one counter in the plurality of counters.

10. The apparatus of claim 8, wherein the integrated circuit is further configured to vary a magnitude of the analog signal represented by a least significant bit of at least one counter in the plurality of counters.

11. The apparatus of claim 8, wherein the first counter is configured to shift data to another counter in the plurality of counters in response to a shift signal.

12. The apparatus of claim 8, further comprising a converter to generate the series of pulses.

13. An apparatus for counting pulses in a series of pulses representing an analog signal, the apparatus comprising:

an integrated circuit comprising a plurality of unit cells, wherein at least one unit cell in the plurality of unit cells comprises;

a plurality of counters operably configured to count at least one pulse in the series of pulses representing the analog signal, wherein at least one counter in the plurality of counters is configured to be switched from a first operating mode to a second operating mode independently of operating modes of the other counters in the plurality of counters;

a converter to generate the series of pulses representing the analog signal; and

a variable capacitance operably coupled to the converter and configured to integrate the analog signal when the at least one counter transitions from the first operating mode to the second operating mode.

14. A method of counting pulses in a series of pulses representing an analog signal in at least one unit cell in an array of unit cells, wherein the at least one unit cell comprises a plurality of counters, the method comprising:

switching at least one counter in the plurality of counters from a first operating mode to a second operating mode independent of operating modes of other counters in the plurality of counters;

changing a count in the at least one counter in response to at least one pulse in the series of pulses; and

changing a magnitude of the analog signal represented by a least significant bit of the at least one counter.

15. The method of claim 14, wherein the first operating mode is a count-up mode and the second operating mode is a count-down mode.

16. The method of claim 14, wherein the first operating mode is a count mode and the second operating mode is a shift mode.

17. The method of claim 16, further comprising:

preventing the at least one counter in the plurality of counters from transferring data to other unit cells in the array of unit cells when the plurality of counters is in the count mode.

18. The method of claim 14, further comprising:

changing an integration period of the at least one counter.

19. The method of claim 14, further comprising:

converting the analog signal into the series of pulses with an analog-to-digital converter (ADC).

20. The method of claim 14, wherein the at least one counter includes a first counter and a second counter, and wherein the method further comprises:

transferring digital data from the first counter to the second counter; and

incrementing or decrementing a count in the second counter based on the digital data.

21. The method of claim 14, wherein the at least one counter includes a first counter and a second counter, and wherein the method further comprises:

counting another pulse in the series of pulses with the second counter;

shifting first digital data from the first counter to a second unit cell in the plurality of unit cells; and

shifting second digital data from the second counter to a third unit cell in the plurality of unit cells.

22. The method of claim 14, further comprising:

storing the analog signal while the at least one counter transitions from the first counting mode to the second counting mode.

23. A method of counting pulses in a series of pulses representing an analog signal in at least one unit cell in an array of unit cells, wherein the at least one unit cell comprises a plurality of counters, the method comprising:

detecting a modulated signal and a local oscillator signal;

generating the analog signal at an intermediate frequency in response to detection of the modulated signal and the local oscillator signal;

switching at least one counter in the plurality of counters from a first operating mode to a second operating mode independent of operating modes of other counters in the plurality of counters; and

changing a count in the at least one counter in response to at least one pulse in the series of pulses.

24. A method of counting pulses in a series of pulses representing an analog signal in at least one unit cell in an array of unit cells, wherein the at least one unit cell includes a first counter and a second counter, the method comprising:

generating in-phase and quadrature control signals;

switching the first counter between a count-up mode and a count-down mode in response to the in-phase control signal;

switching the second counter between the count-up mode and the count-down mode in response to the quadrature control signal; and

changing a count in at least one of the first counter and the second counter in response to at least one pulse in the series of pulses.