×

Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components

  • US 8,606,934 B2
  • Filed: 01/05/2009
  • Issued: 12/10/2013
  • Est. Priority Date: 12/13/2004
  • Status: Active Grant
First Claim
Patent Images

1. A method comprising:

  • asserting a signal to subsequently permit electrical transfer of information, via control flits, between a first agent and a second agent of a link;

    performing initialization of a physical link layer by conveying capabilities and identifiers of components at the first and second agents, wherein the link layer initialization is further performed by exchanging link layer control messages including the control flits; and

    transmitting one or more of the control flits to initialize a component that adheres to a point-to-point (pTp) architecture, wherein each point to point link comprises a pair of uni-directional links between pairs of processing cores, and wherein the control flits support flexible system and socket layer parameters corresponding to a host platform and component types, and the control flits to provide initialization values, wherein the initialization values are used for powering up to avoid multiple warm resets and improve boot time, and eliminating pin limitation associated with computer hardware by conveying the initialization values via the control flits, wherein the information conveyed via the control flits during initialization of the physical layer includes the initialization values including one more of parameters for the link layer, parameters of a protocol layer, and initialization values of the components, wherein the control flits comprise one or more of;

    i) system boot strap processor (SBSP) indicator, built in self-test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,ii) indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature,iii) platform topology index, that may be used by the firmware to obtain values for programming the route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource,iv) indication to a memory controller to preserve the memory contents, andv) indication to an input/output (IO) agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×