Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components
First Claim
1. A method comprising:
- asserting a signal to subsequently permit electrical transfer of information, via control flits, between a first agent and a second agent of a link;
performing initialization of a physical link layer by conveying capabilities and identifiers of components at the first and second agents, wherein the link layer initialization is further performed by exchanging link layer control messages including the control flits; and
transmitting one or more of the control flits to initialize a component that adheres to a point-to-point (pTp) architecture, wherein each point to point link comprises a pair of uni-directional links between pairs of processing cores, and wherein the control flits support flexible system and socket layer parameters corresponding to a host platform and component types, and the control flits to provide initialization values, wherein the initialization values are used for powering up to avoid multiple warm resets and improve boot time, and eliminating pin limitation associated with computer hardware by conveying the initialization values via the control flits, wherein the information conveyed via the control flits during initialization of the physical layer includes the initialization values including one more of parameters for the link layer, parameters of a protocol layer, and initialization values of the components, wherein the control flits comprise one or more of;
i) system boot strap processor (SBSP) indicator, built in self-test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing,ii) indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature,iii) platform topology index, that may be used by the firmware to obtain values for programming the route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource,iv) indication to a memory controller to preserve the memory contents, andv) indication to an input/output (IO) agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent.
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Abstract
Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.
For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
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Citations
14 Claims
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1. A method comprising:
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asserting a signal to subsequently permit electrical transfer of information, via control flits, between a first agent and a second agent of a link; performing initialization of a physical link layer by conveying capabilities and identifiers of components at the first and second agents, wherein the link layer initialization is further performed by exchanging link layer control messages including the control flits; and transmitting one or more of the control flits to initialize a component that adheres to a point-to-point (pTp) architecture, wherein each point to point link comprises a pair of uni-directional links between pairs of processing cores, and wherein the control flits support flexible system and socket layer parameters corresponding to a host platform and component types, and the control flits to provide initialization values, wherein the initialization values are used for powering up to avoid multiple warm resets and improve boot time, and eliminating pin limitation associated with computer hardware by conveying the initialization values via the control flits, wherein the information conveyed via the control flits during initialization of the physical layer includes the initialization values including one more of parameters for the link layer, parameters of a protocol layer, and initialization values of the components, wherein the control flits comprise one or more of; i) system boot strap processor (SBSP) indicator, built in self-test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing, ii) indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature, iii) platform topology index, that may be used by the firmware to obtain values for programming the route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource, iv) indication to a memory controller to preserve the memory contents, and v) indication to an input/output (IO) agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent. - View Dependent Claims (2, 3, 4)
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5. A system that adheres to a point-to-point (pTp) architecture and facilitates initialization comprising:
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a plurality of processing devices and memory devices coupled to a network fabric a physical layer to assert a signal to subsequently to permit electrical transfer of information, via control flits, between a first agent and a second agent of a link of either the plurality of processing devices and memory devices, coupled to the network fabric; a physical link layer, wherein the physical link layers is initialized by conveying capabilities and identifiers of components at the first and second agents, wherein the link layer initialization is further performed by exchanging link layer control messages including the control flits; and the physical layer to transmit one or more of the control flits to initialize a component that adheres to the pTp architecture, wherein each point to point link comprises a pair of uni-directional links between pairs of processing cores, and wherein the control flits support flexible system and socket layer parameters corresponding to a host platform and component types, and the control flits to provide initialization values, wherein the initialization values are used for powering up to avoid multiple warm resets and improve boot time, and eliminating pin limitation associated with computer hardware by conveying the initialization values via the control flits, wherein the information conveyed via the control flits during initialization of the physical layer includes the initialization values including one more of parameters for the link layer, parameters of a protocol layer, and initialization values of the components, wherein the control flits comprise one or more of; i) system boot strap processor (SBSP) indicator, built in self-test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing, ii) indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature, iii) platform topology index, that may be used by the firmware to obtain values for programming the route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource, iv) indication to a memory controller to preserve the memory contents, and v) indication to an input/output (IO) agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent. - View Dependent Claims (6, 7, 8, 9)
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10. An apparatus comprising:
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a plurality of processing devices and memory devices coupled to a network fabric a physical layer to assert a signal to subsequently permit electrical transfer of information, via control flits, between a first agent and a second agent of a link of either the plurality of processing devices and memory devices, coupled to the network fabric; a physical link layer, wherein the physical link layers is initialized by conveying capabilities and identifiers of components at the first and second agents, wherein the link layer initialization is further performed by exchanging link layer control messages including the control flits; and the physical layer to transmit one or more of the control flits to initialize a component that adheres to a point-to-point (pTp) architecture, wherein each point to point link comprises a pair of uni-directional links between pairs of processing cores, and wherein the control flits support flexible system and socket layer parameters corresponding to a host platform and component types, and the control flits to provide initialization values, wherein the initialization values are used for powering up to avoid multiple warm resets and improve boot time, and eliminating pin limitation associated with computer hardware by conveying the initialization values via the control flits, wherein the information conveyed via the control flits during initialization of the physical layer includes the initialization values including one more of parameters for the link layer, parameters of a protocol layer, and initialization values of the components, wherein the control flits comprise one or more of; i) system boot strap processor (SBSP) indicator, built in self-test (BIST), Processor to Platform Clock Ratio, Authentication of external Firmware, Burn in Testing, ii) indication of cores that should remain inactive for avoiding defective cores or implementing licensing restrictions and Capacity on Demand feature, iii) platform topology index, that may be used by the firmware to obtain values for programming the route tables and other interconnect fabric using data from the firmware, non-volatile memory (NVM) or other platform resource, iv) indication to a memory controller to preserve the memory contents, and v) indication to an input/output (IO) agent that the processor socket incorporates bridges, hubs and devices that are logically downstream from the IO agent. - View Dependent Claims (11, 12, 13, 14)
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Specification