Massively multicore processor and operating system to manage strands in hardware

• US 8,607,086 B2
• Filed: 12/21/2011
• Issued: 12/10/2013
• Est. Priority Date: 09/02/2011
• Status: Expired due to Fees

• Current Assignee: Iota Computing, Inc.
• Original Assignee: Iota Computing, Inc.
• Inventors: Cullimore, Ian Henry Stuart
• Primary Examiner(s): Bae, Ji H
• Application Number:
  US13/333,802
• Publication Number:
  US 20130061078A1
• Time in Patent Office: 720 Days
• Field of Search: None
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/06 using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs.

Claims

1. A computing apparatus, comprising:

a set of interconnected central processing units (CPUs), each of the CPUs embedding an operating system (OS), the OS comprising an operating system kernel, the operating system kernel being a state machine based on a network protocol stack; and

at least one of the CPUs further embedding executable instructions for allocating multiple strands to one or more other CPUs of the set of interconnected CPUs.

2. The apparatus of claim 1, wherein the one or more other CPUs includes all other CPUs of the set such that the at least one of the CPUs embeds executable instructions for allocating multiple strands to all other CPUs of the set of interconnected CPUs.

3. The apparatus of claim 1, wherein the one or more other CPUs includes less than all of the other CPUs of the set, any of the CPUs not allocated strands being turned off to conserve power.

4. The apparatus of claim 1, wherein the one or more other CPUs includes less than all of the other CPUs of the set, and wherein any of the CPUs not allocated strands are placed in a sleep mode to conserve power.

5. The apparatus of claim 1, wherein the network protocol stack comprises a User Datagram Protocol/Internet Protocol (UDP/IP) stack such that the OS is a UDP/IP stack state machine or Internet Control Message Protocol (ICMP) stack such that the OS is ICMP stack.

6. The apparatus of claim 1, wherein each of the CPUs comprises a processing unit, a memory and an Input/Output (I/O) interface.

7. The apparatus of claim 6, wherein the memory includes one or more of the following memory types:

a Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Field Programmable Read-Only Memory (FPROM), One-Time Programmable Read-Only Memory (OTPROM), One-Time Programmable Non-Volatile Memory (OTPNVM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM or Flash ROM), the executable instructions for the OS being stored within the one or more memory types wherein all operations for the OS are executed using a Sockets applications programming interface (API).

8. The apparatus of claim 1, further comprising at least one asynchronous clock to serve as an internal clock for the OS.

9. The apparatus of claim 8, wherein the asynchronous clock is configurable to automatically stop when clock cycles are no longer needed.

10. The apparatus of claim 1, wherein a time reference for the OS kernel is based on a Network Time Protocol (NTP), Simple Network Time Protocol (SNTP), or a Precision Time Protocol (PTP).

11. The apparatus of claim 1, wherein the set of interconnected CPUs are interconnected through a bus.

12. The apparatus of claim 1, wherein executable instructions for the operating system are executed through a Sockets applications programming interface (API).

13. The apparatus of claim 1, wherein the OS utilizes a Sockets style API of sockets and ports on Internet Protocol (IP) addresses for handling I/O requests.

14. The apparatus of claim 1, wherein the at least one CPU embedding executable instructions for allocating multiple strands further comprises instructions for generating multiple strands.

15. The apparatus of claim 1, where the set of interconnected CPUs comprises 1000 interconnected CPUs.

16. A method, comprising:

receiving an input/output (I/O) request;

generating one or more strands according to the I/O request;

allocating the one or more strands to one or more central processing units (CPUs) of a set of CPUs, wherein each CPU of the set embeds an operating system (OS) having a kernel based on a network protocol stack; and

processing the one or more strands.

17. The method of claim 16, wherein any of the CPUs not allocated at least one of the strands is turned off to conserve power.

18. The method of claim 16, wherein the network protocol stack comprises a Transmission Control Protocol/Internet Protocol (TCP/IP) stack such that the OS is a TCP/IP stack state machine.

19. The method of claim 16, wherein the network protocol stack comprises a User Datagram Protocol/Internet Protocol (UDP/IP) stack such that the OS is a UDP/IP stack state machine or Internet Control Message Protocol (ICMP) stack such that the OS is ICMP stack.

20. The method of claim 16, wherein at least one of the CPUs of the set of CPUs receives I/O requests, the at least one CPU embedding executable instructions for allocating the multiple strands to a number of the other CPUs of the set of CPUs.

21. The method of claim 16, wherein allocating comprises communicating data via a network interface.

22. The method of claim 16, further comprising assembling results of the processing.

23. The method of claim 16, wherein executable instructions for the operating system are stored in one or more of the following memory types:

Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Field Programmable Read-Only Memory (FPROM), One-Time Programmable Read-Only Memory (OTPROM), One-Time Programmable Non-Volatile Memory (OTP NVM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM or Flash ROM), wherein all operations for the OS are executed using a Sockets applications programming interface (API).

24. A non-transitory computer-readable storage medium having embodied instructions thereon, instructions executable by a processor in a computing device to perform a method, the method comprising:

receiving an input/output (I/O) request;

generating one or more strands according to the I/O request;

allocating the one or more strands to one or more central processing units (CPUs) of a set of CPUs, wherein each CPU of the set embeds an operating system (OS), the OS comprising a kernel that is a state machine based on a network protocol stack; and

processing the one or more strands.