Netlist cell identification and classification to reduce power consumption

• US 8,607,177 B2
• Filed: 04/10/2008
• Issued: 12/10/2013
• Est. Priority Date: 04/10/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Verbeure, Tom
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US12/101,055
• Publication Number:
  US 20090259982A1
• Time in Patent Office: 2,070 Days
• Field of Search: 716/1, 716/2, 716/4, 716/5, 716/8, 716/10, 716/11, 713/322, 713/324, 703/13, 703/14
• US Class Current: 716/109
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Claims

1. A computer implemented synthesis method for a programmable system-on-a-chip integrated circuit device, comprising:

accessing a circuit netlist via the synthesis computer system, the circuit netlist representing a programmable system-on-a-chip integrated circuit design to be realized in physical form; and

modifying a plurality of cells of the circuit netlist by using a netlist cell iterative sorting process, wherein the sorting process functions by;

determining those cells of the circuit netlist that are coupled to a first power domain, wherein the first power domain is configured to remain powered in a standby mode;

determining those cells of the circuit netlist that are coupled to a second power domain, wherein the second power domain is configured to shut down in the standby mode; and

configuring those cells that are coupled to the second power domain to receive power from the second power domain to enable shut down when the integrated circuit device enters standby mode.

2. The method of claim 1, wherein the first power domain is configured to retain power and selected device state data when the second power domain is shut down.

3. The method of claim 1, those cells that are coupled to the second power domain are shut down with reduced leakage current when power to the second power domain is shut down.

4. The method of claim 1, wherein the per cell iterative search functions by examining each cell of the circuit netlist and altering an examined cell upon determining whether the examined cell is coupled to the second power domain.

5. The method of claim 4, wherein the per cell iterative search is complete when each cell of the circuit netlist is examined and no alterations are performed.

6. The method of claim 1, wherein the per cell iterative search is initiated at a functional block within the second power domain and traces those cells that cascade from the functional block.

7. The method of claim 1, wherein the per cell iterative search is initiated at an input output pad providing functionality for the second power domain and traces those cells that cascade from the input output pad.

8. The method of claim 1, wherein the per cell iterative search is configured to ensure cells providing functionality for the first power domain are not altered to be powered by the second power domain.

9. A computer-aided design system for producing an integrated circuit netlist for a programmable system-on-a-chip integrated circuit device, the computer aided design system including a processor coupled to a computer readable memory having computer readable code, which when executed by the processor causes the computer-aided design system to:

examine a circuit netlist, the circuit netlist representing a programmable system-on-a-chip integrated circuit design to be realized in physical form; and

modify a plurality of those cells of the circuit netlist by using a netlist cell iterative sorting process, wherein the sorting process functions by;

determining those cells of the circuit netlist that are coupled to a first power domain, wherein the first power domain is configured to remain powered in a standby mode to retain selected device state data;

determining those cells of the circuit netlist that are coupled to a second power domain, wherein the second power domain is configured to shut down in the standby mode; and

configuring those cells that are coupled to the second power domain to receive power from the second power domain to enable shut down when the integrated circuit device enters standby mode, and wherein the shut down reduces cell leakage current.

10. The computer-aided design system of claim 9, wherein the per cell iterative search functions by examining each cell of the circuit netlist and altering an examined cell upon determining whether the examined cell is coupled to the second power domain.

11. The computer-aided design system of claim 9, wherein the per cell iterative search is complete when each cell of the circuit netlist is examined and no alterations are performed, while ensuring cells providing functionality for the first power domain are not altered to be powered by the second power domain.

12. The computer-aided design system of claim 9, wherein the per cell iterative search is initiated at a functional block within the second power domain and traces those cells that cascade from the functional block, or initiated at an input output pad providing functionality for the second power domain and traces those cells that cascade from the input output pad.

13. The computer aided design system of claim 12, wherein the per cell iterative search identifies cells which provide no functionality in sleep mode.