Energy-focused compiler-assisted branch prediction
First Claim
Patent Images
1. A method for use with a processor, comprising:
- adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime;
removing the control-flow changing instruction from the instruction sequence; and
in hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and (ii) to fetch an instruction corresponding to the path.
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Accused Products
Abstract
A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a control-flow changing instruction. Microarchitecture is configured to use the control information at runtime to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction.
295 Citations
50 Claims
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1. A method for use with a processor, comprising:
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adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime; removing the control-flow changing instruction from the instruction sequence; and in hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and (ii) to fetch an instruction corresponding to the path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system for use with a processor, comprising:
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a machine to execute a compiler (i) to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and (ii) to remove the control-flow changing instruction from the instruction sequence; and microarchitecture to use the control information at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and (ii) to fetch an instruction corresponding to the path, the microarchitecture comprising hardware. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method for use with a processor, comprising:
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adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction; extracting the control information from a buffer prior to the control information entering a pipeline of the processor; and in hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. - View Dependent Claims (24, 25, 26)
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27. A system for use with a processor, comprising:
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a machine to execute a compiler to add control information to an instruction sequence at compile time, the compiler for adding the control information in the instruction sequence prior to a control-flow changing instruction; and microarchitecture; (i) to extract the control information from a buffer prior to the control information entering a pipeline of the processor, and (ii) to use the control information at runtime; (a) to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (b) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path; and (c) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information; wherein the microarchitecture comprises hardware. - View Dependent Claims (28, 29, 30)
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31. A method for use with a processor, comprising:
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adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction; and in hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome being predicted without requiring fetching of the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38)
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39. A system for use with a processor, comprising:
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a machine to execute a compiler to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction; and a microarchitecture to use the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome being predicted without requiring fetching of the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, the microarchitecture comprising hardware, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46)
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47. A method for use with a processor, comprising:
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adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and compile-time comprising a time during which program code is translated into the instruction sequence; at compile-time, removing the control-flow changing instruction from the instruction sequence; and in hardware, using the control information at runtime to predict an outcome of the control-flow changing instruction that was removed at compile-time, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction. - View Dependent Claims (48)
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49. A system for use with a processor, comprising:
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a machine to execute a compiler (i) to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and compile-time comprising a time during which program code is translated into the instruction sequence, and (ii) to remove the control-flow changing instruction from the instruction sequence at compile time; and microarchitecture to use the control information at runtime to predict an outcome of the control-flow changing instruction that was removed at compile-time, the microarchitecture comprising hardware, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction. - View Dependent Claims (50)
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Specification