Reverse MIM capacitor

• US 8,607,424 B1
• Filed: 03/11/2011
• Issued: 12/17/2013
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Korobov, Vladimir, Pohland, Oliver
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US13/046,640
• Time in Patent Office: 1,012 Days
• Field of Search: 29 2541- 2542, 29D/IG.16, 29831-832, 298/52, 298/47, 361/306.3, 361/308.2, 361311-313, 3613214-32125, 438/690, 438/430, 257/532, 257/E29.343, 257/303
• US Class Current: 29/25.42
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

Claims

1. A method, comprising:

forming a lower metal layer above a substrate;

forming a bottom electrode of a metal-insulator-metal (MIM) capacitor above the lower metal layer;

forming a dielectric layer disposed between the lower metal layer and the bottom electrode;

forming a via extending from the lower metal layer to the bottom electrode;

forming an upper metal layer above the lower metal layer and the bottom electrode, wherein the upper metal layer comprises a top electrode of the MIM capacitor and a top metal layer of a pixel stack; and

defining an optical aperture in the pixel stack.

2. The method of claim 1, wherein the upper metal layer comprises an intermediate metal layer of a pixel stack.

3. The method of claim 1, further comprising forming a single intermediate layer between the lower metal layer and the upper metal layer, wherein the single intermediate layer comprises a second dielectric layer, wherein the top electrode of the upper metal layer is disposed above the second dielectric layer to prevent subsequent processing of the second dielectric layer.

4. The method of claim 3, further comprising forming a spacer post adjacent to the bottom electrode and the dielectric layer.

5. The method of claim 1, further comprising forming at least two intermediate layers between the lower metal layer and the upper metal layer, wherein the intermediate layers comprise at least the dielectric layer and an etch stop layer.