Method for fabricating semiconductor device with buried bit lines

• US 8,609,491 B2
• Filed: 06/06/2011
• Issued: 12/17/2013
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hwang, Eui-Seong
• Primary Examiner(s): AU, BAC H
• Application Number:
  US13/153,958
• Publication Number:
  US 20120171846A1
• Time in Patent Office: 925 Days
• Field of Search: 438/156, 438/262, 438/268, 438/424, 438/427, 438/435, 438/666, 438/674, 438/696, 438/700, 438702-704, 438735-736, 438/761
• US Class Current: 438/268
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.

Claims

1. A method for fabricating a semiconductor device, comprising:

etching a substrate to form trenches that separate active regions;

forming an insulation layer having an opening to open a portion of a sidewall of each active region;

forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer;

wherein the forming of the silicon layer pattern comprises;

forming a silicon layer having a seam within the silicon layer,

wherein the silicon layer gap-fills the trenches; and

etching the silicon layer to etch an upper portion of the seam, wherein the etched silicon layer covers the opening;

forming a metal layer over the silicon layer pattern; and

forming a metal silicide layer as buried bit lines, wherein the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.

2. The method of claim 1, wherein the silicon layer is deposited at a temperature ranging from 600°

C. to 900°

C.

3. The method of claim 1, wherein the forming of the silicon layer pattern comprises:

depositing a silicon layer through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process; and

etching the silicon layer.

4. The method of claim 1, wherein the silicon layer pattern includes a polysilicon layer.

5. The method of claim 1, wherein the metal layer includes one selected from the group consisting of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd).

6. The method of claim 1, wherein the forming of the metal silicide layer is performed using a rapid thermal annealing (RTA) method.

7. The method of claim 1, further comprising removing a remained portion of the metal layer, which is not reacted with the silicon layer pattern, after the forming of the metal silicide layer.

8. A method for fabricating a semiconductor device, comprising:

etching a substrate to form trenches that separate active regions;

forming an insulation layer having an opening to open a portion of a sidewall of each active region;

forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer;

wherein the forming of the silicon layer pattern comprises;

forming a silicon layer over the insulation layer to gap-fill the trenches;

performing a primary etch process on the silicon layer;

forming spacers on sidewalls of the insulation layer after the primary etch process; and

performing a secondary etch process on the silicon layer by using the spacers as an etch barrier;

forming a metal layer over the silicon layer pattern; and

forming a metal silicide layer as buried bit lines, wherein the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.

9. The method of claim 8, wherein the silicon layer pattern has a U-shaped cavity after the secondary etch process.

10. A method for fabricating a semiconductor device, comprising:

etching a substrate to form trenches that separate active regions;

forming an insulation layer having an opening to open a portion of a sidewall of each active region;

forming a silicon layer over the insulation layer to gap-fill a portion of each trench and cover the opening in the insulation layer;

forming spacers on portions of sidewalls of the insulation layer;

etching the silicon layer by using the spacers as an etch barrier;

forming a metal layer over the etched silicon layer; and

forming a metal silicide layer as buried bit lines, wherein the metal silicide layer is formed when the metal layer reacts with the silicon layer.

11. The method of claim 10, wherein the forming of the spacers comprises:

forming a spacer layer to be used as the spacers over the portions of the sidewalls of the insulation layer; and

performing an etch-back process on the spacer layer.

12. The method of claim 10, wherein the spacers comprise one selected from the group consisting of an insulation layer, a metal layer, and a metal nitride layer.

13. The method of claim 10, wherein the spacers comprise one selected from the group consisting of a silicon layer, a silicon oxide layer, a silicon nitride layer, TiN, TiAlN, TiW, TiO₂, WSi₂, WN, TaN, TaW and Ta₂O₅.

14. The method of claim 10, wherein in the forming of the silicon layer, the silicon layer comprises a polysilicon layer.

15. The method of claim 10, wherein the silicon layer is deposited through an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

16. The method of claim 10, wherein the metal layer comprises one selected from the group consisting of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd).

17. The method of claim 10, wherein the forming of the metal silicide layer comprises:

performing a primary annealing process to react the metal layer with the silicon layer;

removing a remained portion of the metal layer, which is not reacted with the silicon layer; and

performing a secondary annealing process.

18. The method of claim 10, wherein the metal silicide layer comprises a cobalt silicide layer.

19. The method of claim 10, wherein the forming of the metal silicide layer is performed using a rapid thermal annealing (RTA) method.

20. The method of claim 10, wherein the forming of the metal silicide layer comprises:

performing an annealing process to react the metal layer with the silicon layer; and

removing the metal layer.

21. The method of claim 10, further comprising:

removing the spacers after the forming of the metal silicide layer.

22. The method of claim 10, wherein after the etching of the silicon layer by using the spacers as the etch barrier,

the silicon layer remains on the bottom and sidewalls of each trench and fills the opening.

23. The method of claim 10, wherein after the etching of the silicon layer by using the spacers as the etch barrier,

the silicon layer remains on sidewalls of each trench and fills the opening.

24. The method of claim 10, wherein after the etching of the silicon layer by using the spacers as the etch barrier, the etched silicon layer has a cavity.