On-chip heat spreader

• US 8,609,506 B2
• Filed: 11/19/2012
• Issued: 12/17/2013
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chuan-Yi, Hao, Ching-Chen, Chou, Chen Cheng, Lin, Sheng-Yuan
• Primary Examiner(s): Clark, S. V.
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US13/681,152
• Publication Number:
  US 20130078765A1
• Time in Patent Office: 393 Days
• Field of Search: 438/418, 438/73, 438/106, 438/102, 438/124, 438/127, 257/686, 257/E23.101
• US Class Current: 438/418
• CPC Class Codes: H01L 21/4814 Conductive parts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06519 : including bonding areas providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/08145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/055 : the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Claims

1. A method of forming a semiconductor die, the method comprising:

forming at least one active device in a semiconductor substrate;

forming an inter-metal dielectric (IMD) layer on a first surface of the semiconductor substrate;

forming a metal interconnect structure in the IMD layer;

forming an insulating layer over the IMD layer;

forming a first dielectric layer over the insulating layer;

forming a first bonding pad in the first dielectric layer, the first bonding pad being electrically coupled to the at least one active device through the metal interconnect structure; and

forming a first heat spreader on the insulating layer, the first heat spreader being insulated from the first bonding pad and comprising a structure extending from a center region of the first surface to an outer edge of the first surface, wherein the first heat spreader has a bottom surface coplanar with a bottom surface of the first bonding pad.

2. The method of claim 1, wherein the first bonding pad and the first heat spreader are formed in a same process step.

3. The method of claim 1, wherein the first bonding pad and the first heat spreader are formed in separate process steps.

4. The method of claim 1, wherein the forming the first heat spreader further comprises:

patterning the first dielectric layer to form recesses in the first dielectric layer;

depositing a conductive material in the recesses; and

planarizing the conductive material.

5. The method of claim 1 further comprising:

forming a through substrate via (TSV) through the semiconductor substrate;

forming a second dielectric layer on a second surface of the semiconductor substrate, the second surface being opposite the first surface;

forming a second bonding pad in the second dielectric layer, the second bonding pad being electrically coupled to the TSV; and

forming a second heat spreader in the second dielectric layer, the second heat spreader being insulated from the TSV and the second bonding pad.

6. The method of claim 5, wherein the forming the TSV further comprises:

etching a recess through the first dielectric layer, the insulating layer, the IMD layer, and partially through the semiconductor substrate;

filling the recess with a conductive material; and

thinning the second surface of the semiconductor substrate to expose a portion of the conductive material.

7. The method of claim 5, wherein the TSV is electrically coupled to the at least one active device.

8. The method of claim 5, wherein the second heat spreader further comprises a structure extending from a center region of the second surface to an outer edge of the second surface, wherein the second heat spreader has a bottom surface coplanar with a bottom surface of the second bonding pad.

9. A method of forming a semiconductor device, the method comprising:

forming a first semiconductor die comprising;

forming a first TSV through the first semiconductor die;

forming a first bonding pad on a front-side surface of the first semiconductor die, the first bonding pad being electrically coupled to the first TSV;

forming a first heat spreader on the front-side surface, the first heat spreader being insulated from the first TSV and the first bonding pad, and the first heat spreader having at least one major axis extending along the front-side surface of the first semiconductor die; and

forming a second semiconductor die comprising;

forming a second bonding pad on a front-side surface of the second semiconductor die; and

forming a second heat spreader on the front-side surface of the second semiconductor die, the second heat spreader insulated from the second bonding pad; and

attaching the first semiconductor die to the second semiconductor die, wherein the first and second bonding pads are electrically coupled, and wherein the first and second heat spreaders are physically coupled.

10. The method of claim 9, wherein the second heat spreader having at least one major axis extending along the front-side surface of the second semiconductor die.

11. The method of claim 9, wherein the first semiconductor die comprises one or more active devices, and wherein the first TSV is electrically coupled to at least one of the one or more active devices.

12. The method of claim 9, wherein the forming the first semiconductor die further comprises:

forming a first dielectric layer on the front-side surface of the first semiconductor die, wherein the first bonding pad and the first heat spreader are formed on the first dielectric layer.

13. The method of claim 9, wherein the forming the second semiconductor die further comprises forming a second TSV through the second semiconductor die, wherein the second bonding pad is electrically coupled to the second TSV.

14. The method of claim 9 further comprising:

forming a third bonding pad on a back-side surface of the first semiconductor die, wherein the third bonding pad is electrically coupled to the first TSV; and

forming a third heat spreader on the back-side surface of the first semiconductor die, wherein the third heat spreader is insulated from the third bonding pad.

15. The method of claim 14 further comprising attaching a third semiconductor die to the back-side surface of the first semiconductor die, wherein the third semiconductor die is coupled to the third bonding pad.

16. A method of forming an electronic package, the method comprising:

forming a first semiconductor die comprising;

forming a first TSV through the first semiconductor die;

forming a first bonding pad on a front-side surface of the first semiconductor die;

forming a second bonding pad on a back-side surface of the first semiconductor die, wherein the first TSV is coupled to one of the first and second bonding pads; and

forming a first heat spreader on the front-side surface, the first heat spreader being insulated from the first TSV and the first bonding pad;

forming a second semiconductor die comprising;

forming a third bonding pad on a front-side surface of the second semiconductor die;

attaching the first semiconductor die to a packaging substrate;

attaching the second semiconductor die to the first semiconductor die, wherein the first and third bonding pads are electrically coupled;

attaching a package housing to the packaging substrate, wherein the housing encapsulates the first and second semiconductor dies; and

filling the package housing with a thermal conducting medium.

17. The method of claim 16 further comprising forming a second heat spreader on the front-side surface of the second semiconductor die, wherein the second heat spreader is insulated from the third bonding pad.

18. The method of claim 17, wherein the first heat spreader is physically contacting the second heat spreader, and wherein the thermal conducting medium is contacting the first heat spreader and the second heat spreader.

19. The method of claim 16, wherein the first heat spreader includes an elongated structure having a major axis extending from a center region of the first semiconductor die to an outer edge of the first semiconductor die.

20. The method of claim 16 further comprising:

forming a heat sink, the heat sink comprising conductive material; and

attaching the heat sink to the package housing.