Method of making a memory array with surrounding gate access transistors and capacitors with global staggered local bit lines

• US 8,609,523 B2
• Filed: 12/05/2012
• Issued: 12/17/2013
• Est. Priority Date: 05/13/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/705,744
• Publication Number:
  US 20130095645A1
• Time in Patent Office: 377 Days
• Field of Search: 438/197, 438/238, 438/296, 438/585, 257/329, 257/E29.262
• US Class Current: 438/585
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

Claims

1. A method of fabricating a memory array, the method comprising:

forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;

forming vertical extensions within holes in the sidewall structures, the vertical extensions being generally aligned on top of corresponding first data/bit lines;

forming second data/bit lines extending across and above the vertical extensions and being generally arranged parallel to the first data/bit lines; and

selectively interconnecting overlying second data/bit lines to underlying first data/bit lines by forming local data/bit access transistors and local data/bit access lines generally aligned with and interconnected between the overlying second data/bit lines and the underlying first data/bit lines.

2. The method claim 1 further comprising forming gate structures about the vertical extensions, the gate structures including a gate insulator region generally extending upward and substantially encompassing the vertical extension and a gate conductor generally extending upward and substantially encompassing the gate insulator region.

3. The method of claim 2 wherein the vertical extensions include semiconductive material.

4. A method of fabricating a memory array, the method comprising:

forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;

forming vertical extensions within holes in the sidewall structures, the vertical extensions being aligned generally with the first data/bit lines; and

forming second data/bit lines extending across the vertical extensions, wherein gate conductors encompassing the vertical extensions are arranged with respect to word lines such that the gate conductor is in electrical contact with a respective word line along a first contact surface and along a second contact surface which is arranged substantially opposite the first contact surface.

5. The method claim 4 wherein electrical potential provided via the word lines substantially encircles the vertical extension such that an electric field within the vertical extension is substantially horizontally symmetric at a vertical position of the vertical extension.

6. The method of claim 4 wherein the vertical extensions are generally aligned on top of corresponding first data/bit lines, the second data/bit lines generally arranged parallel to the first data/bit lines and generally arranged above the vertical extensions.

7. The method of claim 4 wherein the second data/bit lines have a higher conductivity than the first data/bit lines.

8. The method of claim 4 further comprising selectively interconnecting overlying second data/bit lines to underlying first data/bit lines by forming local data/bit access transistors and local data/bit access lines generally aligned with and interconnected between the overlying second data/bit lines and the underlying first data/bit lines.

9. The method of claim 8 wherein local data/bit access transistors and local data/bit access lines occur at irregular intervals.

10. The method of claim 8 wherein local data/bit access transistors and local data/bit access lines occur at regular intervals of n such that n is between approximately 32 and approximately 128.

11. A method of fabricating a memory array, the method comprising:

providing a semiconductor substrate;

forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;

forming vertical extensions within holes in the sidewall structures, the vertical extensions being aligned generally with the first data/bit lines; and

forming second data/bit lines extending across the vertical extensions;

wherein gate conductors encompassing the vertical extensions are arranged with respect to word lines such that the gate conductor is in electrical contact with a respective word line along a first contact surface and along a second contact surface which is arranged substantially opposite the first contact surface.

12. The method of claim 11 further comprising forming gate structures about the vertical extensions, the gate structures including a gate insulator region generally extending upward and substantially encompassing the vertical extension and the gate conductor generally extending upward and substantially encompassing the gate insulator region.

13. The method of claim 12 wherein the vertical extensions include semiconductive material.

14. The method of claim 11 wherein electrical potential provided via the word lines substantially encircles the vertical extension such that an electric field within the vertical extension is substantially horizontally symmetric at a vertical position of the vertical extension.

15. The method of claim 11 wherein the vertical extensions are generally aligned on top of corresponding first data/bit lines, the second data/bit lines generally arranged parallel to the first data/bit lines and generally arranged above the vertical extensions.

16. The method of claim 11 wherein the second data/bit lines have a higher conductivity than the first data/bit lines.

17. The method of claim 11 further comprising selectively interconnecting overlying second data/bit lines to underlying first data/bit lines by forming local data/bit access transistors and local data/bit access lines generally aligned with and interconnected between the overlying second data/bit lines and the underlying first data/bit lines.

18. The method of claim 17 wherein local data/bit access transistors and local data/bit access lines occur at regular intervals of n such that n is between approximately 32 and approximately 128.

19. The method of claim 17 wherein local data/bit access transistors and local data/bit access lines occur at irregular intervals.