Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts

• US 8,609,533 B2
• Filed: 03/30/2012
• Issued: 12/17/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Scheiper, Thilo, Flachowsky, Stefan, Hoentschel, Jan
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Lau, Christine C
• Application Number:
  US13/436,323
• Publication Number:
  US 20130256901A1
• Time in Patent Office: 627 Days
• Field of Search: 438/700, 438/702, 438/723, 438/724, 438/735, 438/743, 438/744, 438/758, 438/778, 438/791, 257/632, 257/635, 257/640, 257/649, 257/734
• US Class Current: 438/637
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

Claims

1. A method for fabricating an integrated circuit having a substrate contact, the method comprising:

forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate;

forming a metal silicide region in the silicon substrate exposed by the first trench;

forming a first stress-inducing layer overlying the metal silicide region;

forming a second stress-inducing layer overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;

forming an ILD layer of dielectric material overlying the second stress-inducing layer;

forming a second trench extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region; and

filling the second trench with a conductive material.

2. The method of claim 1, wherein forming the first stress-inducing layer comprises forming the first stress-inducing layer that comprises silicon nitride.

3. The method of claim 1, wherein forming the first stress-inducing layer comprises forming the first stress-inducing layer that has an intrinsic tensile stress.

4. The method of claim 1, wherein forming the first stress-inducing layer comprises forming the first stress-inducing layer using a plasma enhanced chemical vapor deposition (PECVD) process.

5. The method of claim 1, wherein forming the first stress-inducing layer comprises forming the first stress-inducing layer having a thickness of from about 20 to about 150 nm.

6. The method of claim 1, wherein forming the second stress-inducing layer comprises forming the second stress-inducing layer that comprises silicon nitride.

7. The method of claim 1, wherein forming the second stress-inducing layer comprises forming the second stress-inducing layer that has an intrinsic compressive stress.

8. The method of claim 1, wherein forming the second stress-inducing layer comprises forming the second stress-inducing layer using a plasma enhanced chemical vapor deposition (PECVD) process.

9. The method of claim 1, wherein forming the second stress-inducing layer comprises forming the second stress-inducing layer having a thickness of from about 20 to about 150 nm.

10. The method of claim 1, further comprising:

forming an oxide layer overlying the first stress-inducing layer prior to forming the second stress-inducing layer.

11. The method of claim 10, wherein forming the oxide layer comprises forming the oxide layer having a thickness of about 5 to about 20 nm.

12. The method of claim 1, wherein forming the second trench comprises:

etching through the ILD layer using an oxide etching process and using the second stress-inducing layer as an etch stop; and

etching through the first and second stress-inducing layers to the metal silicide region using a nitride etching process.

13. The method of claim 1, wherein filling the second trench comprises filling the second trench with the conductive material that comprises tungsten.

14. A method for fabricating an integrated circuit having a substrate contact, the method comprising:

depositing a first stress-inducing layer overlying a first device region and a second device region of an SOI substrate, wherein the first device region has a first transistor and a second transistor that are formed therein, and wherein the second device region has a first trench that extends through a buried insulating layer to a silicon substrate of the SOI substrate and a metal silicide region that is formed in the silicon substrate exposed by the first trench;

etching a first portion of the first stress-inducing layer that overlies the second transistor while covering a second remaining portion of the first stress-inducing layer that overlies the first transistor and the second device region;

depositing a second stress-inducing layer overlying the first and second device regions, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;

etching a third portion of the second stress-inducing layer that overlies the first transistor while covering a fourth remaining portion of the second stress-inducing layer that overlies the second transistor and the second device region;

depositing an ILD layer of dielectric material overlying the first and second device regions;

etching a second trench in the second device region extending through the ILD layer and the first and second stress-inducing layers that are disposed in the first trench to expose the metal silicide region; and

filling the second trench with a conductive material.

15. The method of claim 14, further comprising:

depositing an oxide layer on the first stress-inducing layer overlying the first and second device regions prior to depositing the second stress-inducing layer.

16. The method of claim 15, wherein etching the third portion of the second stress-inducing layer comprises etching the third portion of the second stress-inducing layer using the oxide layer as an etch stop.

17. The method of claim 15, wherein etching the second trench comprises etching through the ILD layer, the second stress-inducing layer, the oxide layer, and the first stress-inducing layer that are disposed in the first trench.

18. The method of claim 15, wherein etching the second trench comprises:

etching through the ILD layer using an oxide etching process and using the second stress-inducing layer as an etch stop; and

etching through the oxide layer and the first and second stress-inducing layers to the metal silicide region using a nitride etching process.

19. The method of claim 14, wherein depositing the first stress-inducing layer comprises depositing the first stress-inducing layer that has an intrinsic tensile stress, and wherein depositing the second stress-inducing layer comprises depositing the second stress-inducing layer that has an intrinsic compressive stress.

20. An integrated circuit including a substrate contact, the integrated circuit comprising:

a SOI substrate having a semiconductor layer, a silicon substrate, and a buried insulating layer that is disposed between the semiconductor layer and the silicon substrate;

a metal silicide region disposed in the silicon substrate, wherein the SOI substrate has a filled trench formed therein extending through the buried insulating layer to the metal silicide region;

a first stress-inducing layer disposed in the filled trench overlying the metal silicide region;

a second stress-inducing layer disposed in the filled trench overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;

an ILD layer of dielectric material overlying the second stress-inducing layer; and

the substrate contact comprising a conductive material extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region.