Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts
First Claim
1. A method for fabricating an integrated circuit having a substrate contact, the method comprising:
- forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate;
forming a metal silicide region in the silicon substrate exposed by the first trench;
forming a first stress-inducing layer overlying the metal silicide region;
forming a second stress-inducing layer overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;
forming an ILD layer of dielectric material overlying the second stress-inducing layer;
forming a second trench extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region; and
filling the second trench with a conductive material.
5 Assignments
0 Petitions
Accused Products
Abstract
Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
-
Citations
20 Claims
-
1. A method for fabricating an integrated circuit having a substrate contact, the method comprising:
-
forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate; forming a metal silicide region in the silicon substrate exposed by the first trench; forming a first stress-inducing layer overlying the metal silicide region; forming a second stress-inducing layer overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer; forming an ILD layer of dielectric material overlying the second stress-inducing layer; forming a second trench extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region; and filling the second trench with a conductive material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method for fabricating an integrated circuit having a substrate contact, the method comprising:
-
depositing a first stress-inducing layer overlying a first device region and a second device region of an SOI substrate, wherein the first device region has a first transistor and a second transistor that are formed therein, and wherein the second device region has a first trench that extends through a buried insulating layer to a silicon substrate of the SOI substrate and a metal silicide region that is formed in the silicon substrate exposed by the first trench; etching a first portion of the first stress-inducing layer that overlies the second transistor while covering a second remaining portion of the first stress-inducing layer that overlies the first transistor and the second device region; depositing a second stress-inducing layer overlying the first and second device regions, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer; etching a third portion of the second stress-inducing layer that overlies the first transistor while covering a fourth remaining portion of the second stress-inducing layer that overlies the second transistor and the second device region; depositing an ILD layer of dielectric material overlying the first and second device regions; etching a second trench in the second device region extending through the ILD layer and the first and second stress-inducing layers that are disposed in the first trench to expose the metal silicide region; and filling the second trench with a conductive material. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. An integrated circuit including a substrate contact, the integrated circuit comprising:
-
a SOI substrate having a semiconductor layer, a silicon substrate, and a buried insulating layer that is disposed between the semiconductor layer and the silicon substrate; a metal silicide region disposed in the silicon substrate, wherein the SOI substrate has a filled trench formed therein extending through the buried insulating layer to the metal silicide region; a first stress-inducing layer disposed in the filled trench overlying the metal silicide region; a second stress-inducing layer disposed in the filled trench overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer; an ILD layer of dielectric material overlying the second stress-inducing layer; and the substrate contact comprising a conductive material extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region.
-
Specification