Stair step formation using at least two masks

• US 8,609,536 B1
• Filed: 07/06/2012
• Issued: 12/17/2013
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ha, Chang Wan, Wolstenholme, Graham R., Thimmegowda, Deepak
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US13/543,154
• Publication Number:
  US 20140008806A1
• Time in Patent Office: 529 Days
• Field of Search: 438/666, 438/739
• US Class Current: 438/666
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76822 Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Claims

1. A method for forming a memory structure, comprising:

forming a first mask over a conductive material to define a first exposed area; and

forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area; and

removing conductive material from the second exposed area,

wherein an initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

2. The method of claim 1, wherein the second mask is formed of a material that has an etching rate greater than that of the first mask.

3. The method of claim 1, wherein the first mask is a hard mask and the second mask is a photo resist mask.

4. The method of claim 1, further comprising resizing the second mask by an amount such that the second exposed area includes an additional area of at least one more stair step.

5. The method of claim 1, wherein the first dimension is a length, and the second dimension is a width.

6. The method of claim 5, wherein the initial width of the second mask is at least the width of the first exposed area plus a product of a number of stair steps in the stair step structure times an amount by which the width of the second mask is resized to form one stair step.

7. The method of claim 1, wherein forming the second mask over the portion of the first exposed area to define a second exposed area includes forming the second mask centered in one direction within the first exposed area such that the second exposed area has two portions of equal area on opposite ends of the first exposed area.

8. The method of claim 1, wherein forming the second mask over the portion of the first exposed area to define a second exposed area includes forming the second mask offset from center in one direction within the first exposed area such that the second exposed area is at one end of the first exposed area.

9. The method of claim 1, wherein forming the first mask includes forming an opening to define the first exposed area.

10. The method of claim 9, wherein forming the second mask includes forming the second mask completely across the opening in at least one dimension.

11. The method of claim 9, wherein forming the second mask includes forming the second mask to overlap the first mask on opposite edges of the opening.

12. The method of claim 9, wherein forming the opening comprises forming an opening having a non-square shape.

13. The method of claim 12, wherein forming the second mask includes forming the second mask to overlap the first mask at three of four edges of the non-square shape.

14. The method of claim 1, wherein the second exposed area includes two non-contiguous portions.

15. The method of claim 1, wherein the conductive material is a polysilicon material, the polysilicon material being arranged in a stack of materials that includes alternating polysilicon material and oxide material.

16. A method of forming a memory structure, comprising:

forming a first mask over a stack of materials that includes alternating conductive materials and insulating materials, the first mask covering a first area of the stack of materials in which a stair step structure is not to be subsequently formed and not covering a second area of the stack of materials in which the stair step structure is to be subsequently formed;

forming a second mask over a first portion of the second area and over a portion of the first mask; and

removing some of the alternating conductive materials and insulating materials from a second portion of the second area not covered by the first mask or the second mask,

wherein the second mask initially overlaps a dimension of the second area by at least an amount by which the second mask is reduced to form a next stair step times a quantity of stair steps to be formed.

17. The method of claim 16, wherein the second mask still overlaps a portion of the first mask after the last stair step is formed.

18. The method of claim 16, wherein after the last stair step is formed, the second mask still overlaps the dimension of the second area.

19. The method of claim 16, further comprising:

reducing a size of the second mask by removing the amount from each side; and

removing additional alternating conductive materials and insulating materials from a third portion of the second area not covered by the first mask or the second mask having the reduced size, the third portion including the second portion.

20. The method of claim 16, wherein forming the first mask includes forming the first mask over the first and second areas of the stack of materials;

and forming an opening in the first mask over the second area.

21. The method of claim 16, wherein forming the second mask includes forming the second mask centered in one direction within the second area in which a stair step structure is to be formed.

22. A method of forming a memory structure, comprising:

forming a plurality of stacks of columns of alternating conductive materials and insulating materials, the plurality of stacks of columns arranged side-by-side with at least one inner stack of columns being located between two outer stacks of columns;

forming a first mask over the two outer stacks of columns and a first portion of the at least one inner stack of columns;

forming a second mask over a portion of the first mask and a second portion of the at least one inner stack of columns not covered by the first mask; and

removing a first amount of the alternating conductive materials and insulating materials of the at least one inner stack of columns not covered by the first mask or the second mask.

23. The method of claim 22, further comprising:

re-sizing the second mask to cover less than the second portion of the at least one inner stack of columns not covered by the first mask; and

removing a second amount of the alternating conductive materials and insulating materials of the at least one inner stack of columns not covered by the first mask or the second mask to form a stair step structure.

24. The method of claim 23, wherein removing the first amount includes shortening a length of the at least one inner stack of columns to be less than a length of the two outer stacks of columns.

25. The method of claim 24, wherein removing a second amount includes removing the second amount from an end of the at least one inner stack of columns from which the first amount was removed to shorten the length of the at least one inner stack of columns.

26. The method of claim 22, wherein forming a plurality of stacks of columns includes forming a plurality of inner stacks of columns located between the two outer stacks of columns.

27. A method of forming a memory structure, comprising:

forming a plurality of alternating conductive materials and insulating materials;

forming a first mask of hard mask material over the plurality of alternating conductive materials and insulating materials;

patterning the first mask to have an area exposing the plurality of alternating conductive materials and insulating materials;

forming a second mask over the first mask and the area exposing the plurality of alternating conductive materials and insulating materials;

patterning the second mask to expose a first portion of the area exposing the plurality of alternating conductive materials and insulating materials; and

removing a number of the plurality of alternating conductive materials and insulating materials in the first portion of the area exposing the plurality of alternating conductive materials and insulating materials to form at least one stair step,

wherein the second mask is formed to overlap a dimension of the area exposing the plurality of alternating conductive materials and insulating materials by at least an amount by which the second mask is reduced in size during removing the number of the plurality of alternating conductive materials and insulating materials.