Flat panel display device with simplified efficient structure and method of manufacturing the same

• US 8,610,126 B2
• Filed: 03/08/2011
• Issued: 12/17/2013
• Est. Priority Date: 04/01/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Kyung-Min
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/042,986
• Publication Number:
  US 20110241010A1
• Time in Patent Office: 1,015 Days
• Field of Search: 257/59, 257/72
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

Provided are a flat panel display device and a method of manufacturing the same. The flat panel display device includes a first thin-film transistor including a first active layer, a first insulation layer disposed on the first active layer, and a first gate electrode disposed on the first insulation layer; a second thin-film transistor including a second active layer, the first insulation layer disposed on the second active layer, a second insulation layer disposed on the first insulation layer, and a second gate electrode disposed on the second insulation layer, and electrically connected to the first thin-film transistor; and a capacitor electrically connected to the first thin-film transistor and the second thin-film transistor. In the structure as described above, since different numbers of insulation layers are interposed between active layers and gate electrode in each of the first thin-film transistor and the second thin-film transistor, threshold voltages of the first thin-film transistor and the second thin-film transistor are significantly different from each other, and thus it becomes easy to control the threshold voltages of the first thin-film transistor and the second thin-film transistor.

Claims

1. A flat panel display device comprising:

a first thin-film transistor comprising a first active layer, a first insulation layer disposed on the first active layer, and a first gate electrode disposed on the first insulation layer;

a second thin-film transistor comprising a second active layer, wherein the first insulation layer is disposed on the second active layer,

a second insulation layer disposed on and contacting the first insulation layer, and a second gate electrode disposed on the second insulation layer, and electrically connected to the first thin-film transistor;

a pixel electrode disposed to overlap the entire second active layer and the entire second gate electrode and contact a source region or a drain region; and

a capacitor electrically connected to the first thin-film transistor and the second thin-film transistor.

2. The flat panel display device of claim 1, wherein the second insulation layer extends onto the first gate electrode.

3. The flat panel display device of claim 1, wherein the capacitor comprises:

a first electrode disposed on the first insulation layer; and

a second electrode disposed over the second insulation layer,

wherein the second insulation layer is interposed between the first electrode and the second electrode.

4. The flat panel display device of claim 3, wherein the first gate electrode and the first electrode comprise the same material.

5. The flat panel display device of claim 3, wherein the second gate electrode and the second electrode comprise the same material.

6. The flat panel display device of claim 1, wherein the first active layer comprises:

a first channel region that overlaps the first gate electrode and contains a first type impurity; and

and the first source region and first drain region are disposed on opposite sides of the first channel region and contain a second type impurity, wherein the polarity of the second type impurity is opposite to that of the first type impurity.

7. The flat panel display device of claim 6, wherein the first type impurity is an n-type impurity, and the second type impurity is a p-type impurity.

8. The flat panel display device of claim 1, wherein the second active layer comprises:

a second channel region that overlaps the second gate electrode and contains a second type impurity;

a second source region and a second drain region that are disposed on opposite sides of the second channel region and contain a first type impurity, wherein the polarity of the first type impurity is opposite to that of the second type impurity; and

regions with low impurity concentration that are disposed between the second channel region and the second source and drain regions and comprise the first type impurity at a concentration lower than that of the first impurity in the second source and drain regions.

9. The flat panel display device of claim 8, wherein the first type impurity is an n-type impurity, and the second type impurity is a p-type impurity.