Standard cell architecture using double poly patterning for multi VT devices

• US 8,610,176 B2
• Filed: 01/11/2011
• Issued: 12/17/2013
• Est. Priority Date: 01/11/2011
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Patel, Prayag B., Kamal, Pratyush, Vang, Foua, Gan, Chock H., Swamynathan, Chethan, Chidambaram, Pr
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): SHOOK, DANIEL P
• Application Number:
  US13/004,460
• Publication Number:
  US 20120180016A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/202, 257/204, 257/208, 257/E27.001, 257/E21.575, 438/128, 438/587, 716/119, 716/121
• US Class Current: 257/202
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.

Claims

1. An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds, comprising:

a first set of polylines associated with a first channel length, wherein each polyline within the first set of polylines is separated by a substantially constant pitch;

a second set of polylines associated with a second channel length and aligned with the first set of polylines, wherein each polyline within the second set of polylines is laterally separated by the substantially constant pitch, and wherein the first channel length is different from the second channel length;

a first active region below the first set of polylines; and

a second active region below the second set of polylines, wherein the first active region and the second active region are separated by a distance of less than 170 nm.

2. The apparatus of claim 1, wherein the distance separating the first active region and the second active region is approximately 135 nm.

3. The apparatus of claim 1, wherein the first set of polylines and the second set of polylines are arranged such that centers of each respective polyline are aligned.

4. The apparatus of claim 1, wherein the first channel length is in a range between 20 nm and 30 nm.

5. The apparatus of claim 4, wherein the second channel length is in a range between 30 nm and 40 nm.

6. The apparatus of claim 1, wherein a distance between an edge of the first set of polylines and an edge of the first active region is approximately 31.5 nm.

7. The apparatus of claim 1, wherein a distance between an edge of the second set of polylines and an edge of the second active region is approximately 31.5 nm.

8. The apparatus of claim 1, wherein the substantially constant pitch is approximately 140 nm.

9. The apparatus of claim 1, wherein a first portion and a second portion of the polylines are aligned with each other on a per polyline basis.

10. The apparatus of claim 1, integrated into a device selected from a group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a computer, and at least one semiconductor die.

11. The apparatus of claim 1, wherein the first set of polylines and the second set of polylines comprise a plurality of polylines that are formed into the first channel length and the second channel length using a first masking, and wherein the plurality of polylines are separated into the first set of polylines and the second set of polylines using a second masking.

12. A plurality of devices associated with a standard cell architecture and fabricated by a process comprising:

providing a plurality of polylines over a first active region and a second active region, wherein each polyline is separated by a substantially constant pitch, and further wherein the first active region and the second active region are separated by a distance of less than 170 nm;

forming the plurality of polylines so that each polyline is associated with a first channel length and a second channel length, wherein the first channel length is different from the second channel length; and

separating the plurality of polylines into a first set of polylines and a second set of polylines, wherein the first set of polylines is associated with the first channel length, and the second set of polylines is associated with the second channel length.

13. The plurality of devices of claim 12, wherein the forming further comprises:

using a first masking to separate the plurality of polylines into the plurality of polylines into the first channel length and the second channel length.

14. The plurality of devices of claim 13, wherein the separating further comprises:

using a second masking to form the first set of polylines and the second set of polylines.

15. The plurality of devices of claim 12, wherein the distance separating the first active region and the second active region is approximately 135 nm.

16. The plurality of devices of claim 12, wherein the first channel length is in a range between 20 nm and 30 nm.

17. The plurality of devices of claim 16, wherein the second channel length is in a range between 30 nm and 40 nm.

18. The plurality of devices of claim 17, wherein the substantially constant pitch is approximately 140 nm.

19. The plurality of devices of claim 17, wherein the first set of polylines and the second set of polylines are arranged such that centers of each respective polyline are aligned.

20. The plurality of devices of claim 12, wherein at least one of a distance between an edge of the first set of polylines and an edge of the first active region or a distance between an edge of the second set of polylines and an edge of the second active region is approximately 31.5 nm.

21. The plurality of devices of claim 12, wherein a first portion and a second portion of the polylines are aligned with each other on a per polyline basis.

22. A process for fabricating a plurality of devices associated with a standard cell architecture, comprising:

providing a plurality of polylines over a first active region and a second active region, wherein each polyline is separated by a substantially constant pitch, and further wherein the first active region and the second active region are separated by a distance of less than 170 nm;

forming the plurality of polylines so that each polyline is associated with a first channel length and a second channel length, wherein the first channel length is different from the second channel length; and

separating the plurality of polylines into a first set of polylines and a second set of polylines, wherein the first set of polylines is associated with the first channel length, and the second set of polylines is associated with the second channel length.