Inter-poly dielectric in a shielded gate MOSFET device

• US 8,610,205 B2
• Filed: 03/16/2011
• Issued: 12/17/2013
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean E.
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): KIM, SU C
• Application Number:
  US13/049,655
• Publication Number:
  US 20120235229A1
• Time in Patent Office: 1,007 Days
• Field of Search: 257/139, 257/203, 257/213, 257/330, 257/332, 257/333, 257/678, 257/E29.2, 257/E29.201, 257/E21.655, 438/151, 438/153, 438/259, 438/270, 438/271, 438/275, 438/315, 438/587
• US Class Current: 257/333
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.

Claims

1. An apparatus, comprising:

a shield dielectric disposed within a trench aligned along an axis and disposed within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric and aligned along the axis;

a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis, the plane intersecting the shield electrode;

a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode;

a gate dielectric having a first portion disposed directly on the first inter-poly dielectric; and

a gate electrode disposed above the shield electrode and insulated from the shield electrode by at least the gate dielectric, the gate dielectric having a second portion disposed directly in contact with the gate electrode and disposed directly in contact with a sidewall of the trench.

2. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the portion of the first inter-poly dielectric is disposed between a second portion of the second inter-poly dielectric intersecting the plane and the first portion of the second inter-poly dielectric.

3. The apparatus of claim 1, wherein the portion of the first inter-poly dielectric and the portion of the second inter-poly dielectric are disposed lateral to the axis and are disposed above the shield dielectric.

4. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the second inter-poly dielectric has a second portion disposed between the portion of the first inter-poly dielectric and the shield dielectric.

5. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the second inter-poly dielectric has a second portion disposed between the shield electrode and the portion of the gate dielectric.

6. The apparatus of claim 1, wherein the first inter-poly dielectric is a different type of dielectric than the second inter-poly dielectric.

7. The apparatus of claim 1, wherein the first inter-poly dielectric is a deposited oxide, and the second inter-poly dielectric is a thermally grown oxide.

8. The apparatus of claim 1, wherein the gate dielectric is a thermally grown oxide, and the shield dielectric is at least one of a thermally grown oxide or a deposited oxide.

9. The apparatus claim 1, wherein the first portion of the gate dielectric is disposed directly on the portion of the second inter-poly dielectric.

10. An apparatus, comprising:

a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric and aligned along the axis;

an inter-poly dielectric having a portion disposed below a top surface of the shield electrode and intersecting a plane orthogonal to the axis, the plane intersecting the shield electrode, the portion of the shield dielectric is in direct contact with the shield electrode and is in direct contact with a sidewall of the trench;

a gate dielectric having a first portion disposed directly on the inter-poly dielectric; and

a gate electrode disposed above the shield electrode and insulated from the shield electrode by at least the gate dielectric, the gate dielectric having a second portion disposed directly in contact with the gate electrode and disposed directly in contact with a sidewall of the trench.

11. The apparatus of claim 10, wherein the portion of the inter-poly dielectric is disposed between the gate dielectric and the shield dielectric such that the gate dielectric is isolated from the shield dielectric.

12. The apparatus of claim 10, wherein the portion of the inter-poly dielectric is a first portion, the sidewall of the trench has a first location intersecting a line orthogonal to the axis and has a second location intersecting the line, the inter-poly dielectric has a second portion that extends along the line from the first location to the second location.

13. An apparatus, comprising:

a shield dielectric disposed within a trench within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric;

an inter-poly dielectric having a first portion coupled to the shield dielectric and a second portion coupled to the shield electrode, the inter-poly dielectric having a top surface defining a curve curving in a same direction as at least a portion of a curve of a top surface of the shield electrode;

a gate dielectric having a first portion disposed directly on the top surface of the inter-poly dielectric; and

a gate electrode disposed above the shield electrode and insulated from the shield electrode by at least the gate dielectric, the gate dielectric having a second portion disposed directly in contact with the gate electrode and disposed directly in contact with a sidewall of the trench.

14. The apparatus of claim 13, wherein the trench is aligned along an axis, the shield dielectric has a portion intersecting a plane orthogonal to the axis and is disposed between the inter-poly dielectric and the sidewall of the trench, the plane intersects the shield electrode, the portion of the shield dielectric is in direct contact with the inter-poly dielectric and is in direct contact with the sidewall of the trench.

15. The apparatus claim 13, wherein the first portion of the gate dielectric is disposed directly on the portion of the shield dielectric.

16. The apparatus of claim 13, wherein the inter-poly dielectric is a first deposited oxide, the gate dielectric is a first thermally grown oxide, and the shield dielectric is at least one of a second thermally grown oxide or a second deposited oxide.

17. The apparatus of claim 13, wherein the top surface of the inter-poly dielectric, the shield electrode, and the gate dielectric are aligned along a longitudinal axis,

the first portion of the inter-poly dielectric is disposed adjacent to a wall of the shield electrode.

18. The apparatus of claim 13, wherein the inter-poly dielectric, when deposited, has a thickness that is less than a thickness of the shield dielectric disposed on the shield electrode.

19. The apparatus of claim 13, wherein the first portion of the gate dielectric is coupled to at least a portion of the shield dielectric.

20. A method, comprising:

forming a shield electrode within a shield dielectric disposed within a trench of an epitaxial layer of a semiconductor, the trench being aligned vertically along an axis;

forming, within the trench, a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis, the plane intersecting the shield electrode;

forming, within the trench, a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode; and

forming a gate dielectric having a first portion disposed directly on the first inter-poly dielectric; and

forming a gate electrode disposed above the shield electrode and insulated from the shield electrode by at least the gate dielectric, the gate dielectric having a second portion disposed directly in contact with the gate electrode and disposed directly in contact with a sidewall of the trench.

21. The method of claim 20, wherein the portion of the second inter-poly dielectric is a first portion, and the portion of the first inter-poly dielectric is disposed between a second portion of the second inter-poly dielectric intersecting the plane and the first portion of the second inter-poly dielectric.

22. The method of claim 20, wherein the portion of the first inter-poly dielectric and the portion of the second inter-poly dielectric are disposed lateral to the axis and are disposed above the shield dielectric.