Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit
First Claim
1. A field effect transistor comprising:
- a semiconductor layer having a top surface;
an isolation structure in said semiconductor layer at said top surface;
a gate structure on said top surface offset from said isolation structure, said gate structure having gate sidewalls;
sidewall spacers on said top surface positioned laterally immediately adjacent to said gate sidewalls, said semiconductor layer comprising;
a channel region below said gate structure;
source/drain extension regions on opposing sides of said channel region, each source/drain extension region extending vertically from said top surface to a first depth below said top surface and comprising a first end portion adjacent to said channel region, a second end portion adjacent to said isolation structure and a center portion positioned laterally between said first end portion and said second end portion; and
source/drain regions on said opposing sides of said channel region, each source/drain region comprising;
a first section extending vertically through said first end portion of a source/drain extension region to a second depth below said first depth; and
a second section extending vertically through said second end portion of said source/drain extension region to said second depth;
first dielectric layers on said top surface aligned above and abutting said center portion of each of said source/drain extension regions, respectively;
second dielectric layers above and abutting said first dielectric layers, respectively, each second dielectric layer extending laterally onto said top surface above said first section of a source/drain region to an outer edge of a sidewall spacer adjacent to said gate structure, and further extending laterally onto said top surface above said second section of said source/drain region; and
metal silicide layers on said top surface above said second section of each of said source/drain regions, each metal silicide layer being positioned laterally immediately adjacent to a second dielectric layer.
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Accused Products
Abstract
Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.
16 Citations
10 Claims
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1. A field effect transistor comprising:
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a semiconductor layer having a top surface; an isolation structure in said semiconductor layer at said top surface; a gate structure on said top surface offset from said isolation structure, said gate structure having gate sidewalls; sidewall spacers on said top surface positioned laterally immediately adjacent to said gate sidewalls, said semiconductor layer comprising; a channel region below said gate structure; source/drain extension regions on opposing sides of said channel region, each source/drain extension region extending vertically from said top surface to a first depth below said top surface and comprising a first end portion adjacent to said channel region, a second end portion adjacent to said isolation structure and a center portion positioned laterally between said first end portion and said second end portion; and source/drain regions on said opposing sides of said channel region, each source/drain region comprising; a first section extending vertically through said first end portion of a source/drain extension region to a second depth below said first depth; and a second section extending vertically through said second end portion of said source/drain extension region to said second depth; first dielectric layers on said top surface aligned above and abutting said center portion of each of said source/drain extension regions, respectively; second dielectric layers above and abutting said first dielectric layers, respectively, each second dielectric layer extending laterally onto said top surface above said first section of a source/drain region to an outer edge of a sidewall spacer adjacent to said gate structure, and further extending laterally onto said top surface above said second section of said source/drain region; and metal silicide layers on said top surface above said second section of each of said source/drain regions, each metal silicide layer being positioned laterally immediately adjacent to a second dielectric layer. - View Dependent Claims (2, 3, 4, 5)
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6. An integrated circuit comprising:
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an input/output (I/O) pad; and an input/output (I/O) pad driver connected in series between said input/output (I/O) pad and ground, said input/output (I/O) pad driver comprising a single N-type self-protected electrostatic discharge field effect transistor comprising; a semiconductor layer having a top surface; an isolation structure in said semiconductor layer at said top surface; a gate structure on said top surface offset from said isolation structure, said gate structure having gate sidewall; sidewall spacers on said top surface positioned laterally immediately adjacent to said gate sidewalls, said semiconductor layer comprising; a channel region below said gate structure; source/drain extension regions on opposing sides of said channel region, each source/drain extension region extending vertically from said top surface to a first depth below said top surface and comprising a first end portion adjacent to said channel region, a second end portion adjacent to said isolation structure and a center portion positioned laterally between said first end portion and said second end portion; and source/drain regions on said opposing sides of said channel region, each source/drain region comprising; a first section extending vertically through said first end portion of a source/drain extension region to a second depth below said first depth; and a second section extending vertically through said second end portion of said source/drain extension region to said second depth; first dielectric layers on said top surface aligned above and abutting said center portion of each of said source/drain extension regions, respectively; second dielectric layers above and abutting said first dielectric layers, respectively, each second dielectric layer extending laterally onto said top surface above said first section of a source/drain region to an outer edge of a sidewall spacer adjacent to said gate structure, and further extending laterally onto said top surface above said second section of said source/drain region; and metal silicide layers on said top surface above said second section of each of said source/drain regions and positioned laterally immediately adjacent to a second dielectric layer. - View Dependent Claims (7, 8, 9, 10)
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Specification