Hybrid MOSFET structure having drain side schottky junction

• US 8,610,233 B2
• Filed: 03/16/2011
• Issued: 12/17/2013
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Kulkarni, Pranita, Shahidi, Ghavam G.
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): KIM, SU C
• Application Number:
  US13/049,491
• Publication Number:
  US 20120235239A1
• Time in Patent Office: 1,007 Days
• Field of Search: 257/213, 257/288, 257/368, 257/369, 257/377, 257/382, 257/384, 257/413, 257/414, 257/428, 257/431, 257/449, 257/453, 257/454, 257/455, 257/456, 257/471, 257/485, 257/486, 257/E29.156, 257/E29.161, 257/E21.006, 257/E21.151, 257/E21.164, 257/E21.165, 257/E21.493, 257/E21.634, 257/E21.619, 438/570, 438/571, 438/572, 438/573, 438/576, 438/580, 438/581, 438/582, 438/583, 438/630, 438/648, 438/651, 438/664
• US Class Current: 257/454
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.

Claims

1. A method of forming a transistor device, the method comprising:

forming a patterned gate structure over a semiconductor substrate;

forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure; and

forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact;

wherein a top surface of the Schottky contact of the drain side corresponds to a top surface of the semiconductor substrate.

2. The method of claim 1, further comprising selectively growing an epitaxial semiconductor layer only on the source side of the gate structure so as to form the raised source region.

5. The method of claim 2, wherein forming the raised source region further comprises:

performing an angled implant so as to alter crystal properties of portions of the semiconductor substrate receiving implanted species therein, corresponding to the drain side of the gate structure; and

growing the epitaxial semiconductor layer only on the source side of the gate structure, unaltered by the angled implant, so as to form the raised source region.

6. The method of claim 5, wherein the implanted species comprises an neutral dopant species selected to amorphize the semiconductor substrate so as to prevent epitaxial semiconductor material growth thereon.

13. The method of claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

3. A method of forming a transistor device, the method comprising:

forming a patterned gate structure over a semiconductor substrate;

forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure by selectively growing an epitaxial semiconductor layer only on the source side of the gate structure so as to form the raised source region; and

forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact;

wherein forming the raised source region further comprises;

forming a hardmask layer over the patterned gate structure and the semiconductor substrate;

performing an angled implant so as to alter etch properties of portions the hardmask layer receiving implanted species therein;

removing the portions of the hardmask altered by the angled implant, so as to expose a portion of the semiconductor substrate corresponding to the source side of the gate structure; and

growing the epitaxial semiconductor layer only on the source side of the gate structure so as to form the raised source region.

4. The method of claim 3, wherein the angled implant comprises an electrically neutral species implanted under energy and angle conditions designed to localize the species into the hardmask layer.

7. A method of forming a transistor device, the method comprising:

forming a patterned gate structure over a semiconductor substrate;

forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure;

forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact; and

growing an epitaxial semiconductor layer on the semiconductor substrate and thereafter selectively removing portions of the epitaxial semiconductor layer such that remaining portions thereof are present only on the source side of the gate structure so as to form the raised source region.

8. The method of claim 7, wherein forming the raised source region further comprises:

growing an epitaxial semiconductor layer on the semiconductor substrate;

performing an angled implant so as to alter etch properties of portions the epitaxial semiconductor layer receiving implanted species therein; and

removing the portions of the epitaxial semiconductor layer altered by the angled implant, so as to leave remaining portions thereof only on the source side of the gate structure.

9. The method of claim 8, wherein the angled implant also modifies etch properties of portions of a spacer material of the patterned gate structure receiving implanted species therein.

10. The method of claim 9, further comprising removing a portion of a drain sidewall spacer of the patterned gate structure.

11. The method of claim 7, wherein forming the raised source region further comprises:

growing an epitaxial semiconductor layer on the semiconductor substrate;

forming a hardmask layer over the patterned gate structure and the epitaxial semiconductor layer;

performing an angled implant so as to alter etch properties of portions the hardmask layer receiving implanted species therein;

removing the portions of the hardmask altered by the angled implant, so as to expose a portion of the epitaxial semiconductor layer corresponding to the source side of the gate structure; and

removing the exposed portions of the epitaxial semiconductor layer, so as to leave remaining portions thereof only on the source side of the gate structure.

12. The method of claim 11, wherein the angled implant comprises an electrically neutral species implanted under energy and angle conditions designed to localize the species into the hardmask layer.

15. The method of claim 9, further comprising removing a portion of a drain sidewall spacer of the patterned gate structure.

14. A method of forming a transistor device, the method comprising:

forming a patterned gate structure over a semiconductor substrate;

forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure; and

forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact

wherein the semiconductor substrate comprises an extremely thin silicon-on-insulator (ETSOI) substrate, having a thickness range of about 4 nanometers (nm) to about 12 nm, and wherein forming the silicide contact on the drain side of the gate structure to define the Schottky contact results in consumption of substantially the entire thickness of the ETSOI substrate.

16. A transistor device, comprising:

a patterned gate structure formed over a semiconductor substrate;

a raised source region formed over the semiconductor substrate adjacent a source side of the gate structure; and

silicide contacts formed on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact;

wherein a top surface of the Schottky contact of the drain side corresponds to a top surface of the semiconductor substrate.

17. The device of claim 16, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

18. A transistor device, comprising:

a patterned gate structure formed over a semiconductor substrate;

a raised source region formed over the semiconductor substrate adjacent a source side of the gate structure; and

silicide contacts formed on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure, thereby defining a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact;

wherein the semiconductor substrate comprises an extremely thin silicon-on-insulator (ETSOI) substrate, having a thickness range of about 4 nanometers (nm) to about 12 nm, and wherein the silicide contact on the drain side of the gate structure to define the Schottky contact extends substantially through the entire thickness of the ETSOI substrate.

19. An integrated circuit device, comprising:

a first transistor and a second transistor formed over a semiconductor substrate, the first transistor comprising a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact; and

the second transistor having both raised source side and drain side ohmic contacts;

wherein a top surface of the Schottky contact of the drain side of the first transistor corresponds to a top surface of the semiconductor substrate.

20. The device of claim 19, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate.

21. An integrated circuit device, comprising:

a first transistor and a second transistor formed over a semiconductor substrate, the first transistor comprising a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact; and

the second transistor having both raised source side and drain side ohmic contacts;

wherein the semiconductor substrate comprises an extremely thin silicon-on-insulator (ETSOI) substrate, having a thickness range of about 4 nanometers (nm) to about 12 nm, and wherein a silicide contact on a drain side of a gate structure of the first transistor extends substantially through the entire thickness of the ETSOI substrate.