Trench MOSFET with integrated Schottky barrier diode

• US 8,610,235 B2
• Filed: 09/22/2011
• Issued: 12/17/2013
• Est. Priority Date: 09/22/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Calafut, Daniel, Su, Yi, Kim, Jongoh, Chang, Hong, Yilmaz, Hamza, Ng, Daniel S.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): INOUSSA, MOULOUCOULAY
• Application Number:
  US13/241,126
• Publication Number:
  US 20130075808A1
• Time in Patent Office: 817 Days
• Field of Search: 257/E29.201, 257/E29.257, 257/E29.262, 257/E29.26, 257/E21.629, 257/334, 257/77, 257/168, 257/266, 257/267, 257/279, 257/280, 257/339, 257/409, 257/653, 257/654, 257/E29.159, 257471-486, 257487-496
• US Class Current: 257/471
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

Claims

1. A Schottky diode comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer of the first conductivity type and being lightly doped formed on the semiconductor substrate;

first and second trenches formed in the semiconductor layer, the first and second trenches being lined with a thin dielectric layer and being filled partially with only one trench conductor layer, remaining portions of the first and second trenches being filled with a first dielectric layer; and

a Schottky metal layer formed on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction,

wherein the Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode, and the trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode, the trench conductor layer in each of the first and second trenches being insulated by the first dielectric layer in the respective trenches and being physically isolated from the Schottky metal layer forming the anode of the Schottky diode.

2. The Schottky diode of claim 1, wherein the first and second trenches each has a first trench depth, the first trench conductor layer extends up to about half or less than half of the first trench depth.

3. The Schottky diode of claim 1, wherein the Schottky metal layer is formed on the semiconductor layer overlaying a portion of the width or the entire width of the semiconductor layer from the first trench to the second trench.

4. The Schottky diode of claim 1, further comprising:

a plurality of well regions of a second conductivity type formed in a top portion of the semiconductor layer between the first trench and the second trench, the plurality of well regions being spaced apart in a longitudinal direction parallel to the longitudinal axis of the first and second trenches,

wherein the Schottky metal layer is formed overlying the plurality of well regions and the semiconductor layer between the plurality of well regions.

5. The Schottky diode of claim 4, wherein the Schottky metal layer is formed on the semiconductor layer and the plurality of well regions overlaying a portion of the width or the entire width of the semiconductor layer and the well regions from the first trench to the second trench.

6. The Schottky diode of claim 4, further comprising:

a plurality of contact plugs, each contact plug being formed in a respective well region,

wherein the Schottky metal layer is formed overlying the plurality of well regions, the plurality of contact plugs and the semiconductor layer between the plurality of well regions, the Schottky metal layer forming an ohmic contact with the plurality of contact plugs.

7. The Schottky diode of claim 6, further comprising:

a plurality of contact diffusion regions of the second conductivity type, each contact diffusion region being formed in a respective well region underneath a respective contact plug.

8. The Schottky diode of claim 6, wherein the Schottky metal layer is formed on the semiconductor layer, the plurality of well regions and the plurality of contact plugs and covers a portion of the width or the entire width of the semiconductor layer and the well regions from the first trench to the second trench.

9. The Schottky diode of claim 1, further comprising:

a shallow compensation implant of a second conductivity type applied at the top surface of the semiconductor layer between the first and second trenches, the shallow compensation implant being applied to adjust the forward bias voltage of the Schottky diode.

10. The Schottky diode of claim 1, further comprising:

a deep pocket compensation implant of a second conductivity type formed in the semiconductor layer between the first and second trenches and at a depth away from the top surface of the semiconductor layer, the deep pocket compensation implant being applied to reduce leakage current of the Schottky diode.

11. The Schottky diode of claim 1, further comprising:

a plurality of well regions of a second conductivity type formed in a top portion of the semiconductor layer between the first trench and the second trench, the plurality of well regions being spaced apart in a longitudinal direction parallel to the longitudinal axis of the first and second trenches,

wherein the Schottky metal layer is formed on a top surface of the semiconductor layer between the first trench and the second trench and overlies only the semiconductor layer between the plurality of well regions.

12. The Schottky diode of claim 1, further comprising:

a plurality of well regions of a second conductivity type formed in a top portion of the semiconductor layer between the first trench and the second trench, the plurality of well regions being spaced apart in a longitudinal direction parallel to the longitudinal axis of the first and second trenches; and

an edge termination diffusion region of the second conductivity type formed in the semiconductor layer along a perimeter bounded by the first and second trenches and adjacent well regions,

wherein the Schottky metal layer is formed overlying the semiconductor layer in an area bounded by the edge termination diffusion region.

13. The Schottky diode of claim 1, wherein the Schottky metal layer comprises a titanium nitride layer.

14. The Schottky diode of claim 1, wherein the semiconductor layer comprises an epitaxial layer of the first conductivity type.

15. The Schottky diode of claim 4, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

16. The Schottky diode of claim 1, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate of the first conductivity type.

17. A semiconductor device comprising a field effect transistor and a Schottky diode, the semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a semiconductor layer of the first conductivity type and being lightly doped formed on the semiconductor substrate;

first and second trenches formed in the semiconductor layer, the first and second trenches being lined with a thin dielectric layer and being filled with a first trench conductor layer being the only trench conductor layer in the first and second trenches, the first trench conductor layer filling a portion of each of the first and second trenches, remaining portions of the first and second trenches being filled with a first dielectric layer;

a Schottky metal layer formed on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction;

a third trench formed in the semiconductor layer, the third trench being lined with the thin dielectric layer and being filled with the first trench conductor layer and a second trench conductor layer, the first trench conductor layer being insulated from the second trench conductor layer by an inter-layer dielectric layer, the first trench conductor layer filling a portion of the third trench and the second trench conductor layer extending from the inter-layer dielectric to near a top surface of the third trench;

a first well region of a second conductivity type formed in a top portion of the semiconductor layer adjacent the third trench, the first well region extending to a depth near a bottom edge of the second trench conductor layer formed in the third trench; and

a heavily doped source region of the first conductivity type formed in the first well region adjacent to the sidewall of the third trench,

wherein the Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode;

wherein the field effect transistor is formed with the semiconductor substrate as a drain electrode, the second trench conductor layer in the third trench as the gate electrode, the first well region as the body region, the heavily doped source region as the source electrode, and the first trench conductor layer in the third trench as a gate shielding electrode; and

wherein the first trench conductor layer in the third trench is electrically connected to the source electrode and the first trench conductor layer in each of the first and second trenches are electrically connected to the anode of the Schottky diode, the first trench conductor layer in each of the first and second trenches being insulated by the first dielectric layer in the respective trenches and being physically isolated from the Schottky metal layer forming the anode of the Schottky diode.

18. The semiconductor device of claim 17, wherein the first, second and third trenches have a first trench depth, the first trench conductor layer extends up to about half or less than half of the first trench depth.

19. The semiconductor device of claim 17, further comprising:

a plurality of well regions of the second conductivity type formed in a top portion of the semiconductor layer between the first trench and the second trench, the plurality of well regions being spaced apart in a longitudinal direction parallel to the longitudinal axis of the first and second trenches,

wherein the Schottky metal layer is formed overlying the plurality of well regions and the semiconductor layer between the plurality of well regions.

20. The semiconductor device of claim 19, wherein the plurality of well regions have the same doping concentration and the same depth as the first well region.

21. The semiconductor device of claim 19, further comprising:

a plurality of contact plugs, each contact plug being formed in a respective one of the plurality of well regions,

wherein the Schottky metal layer is formed overlying the plurality of well regions, the plurality of contact plugs and the semiconductor layer between the plurality of well regions, the Schottky metal layer forming an ohmic contact with the plurality of contact plugs.

22. The semiconductor device of claim 21, further comprising:

a plurality of contact diffusion regions of the second conductivity type, each contact diffusion region being formed in a respective well region underneath a respective contact plug.

23. The semiconductor device of claim 17, further comprising:

a shallow diffusion region of the second conductivity type formed at the top surface of the semiconductor layer between the first and second trenches.

24. The semiconductor device of claim 17, further comprising:

a deep pocket diffusion region of the second conductivity type formed in the semiconductor layer between the first and second trenches and at a depth away from the top surface of the semiconductor layer.

25. The semiconductor device of claim 17, wherein the semiconductor layer comprises an epitaxial layer of the first conductivity type.

26. The semiconductor device of claim 17, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

27. The semiconductor device of claim 17, wherein the semiconductor substrate comprises a heavily doped N-type semiconductor substrate.