Integrated circuit with multi recessed shallow trench isolation

• US 8,610,240 B2
• Filed: 07/16/2010
• Issued: 12/17/2013
• Est. Priority Date: 10/16/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tsung-Lin, Chang, Chang-Yun
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US12/838,264
• Publication Number:
  US 20110089526A1
• Time in Patent Office: 1,250 Days
• Field of Search: 257/510, 257/506, 257/544, 438/196
• US Class Current: 257/510
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

Claims

1. An integrated circuit comprising:

a substrate;

at least two pairs of adjacent shallow trench isolation (STI) structures formed in the substrate, wherein each pair of adjacent STI structures has a first STI structure formed to a first bottom depth at a first distance from a top surface of the substrate and a second STI structure formed to a second bottom depth at a second distance from the top surface of the substrate, wherein the first depth and the second depth are different depths;

an oxide fill disposed in each pair of adjacent STI structures, wherein the oxide fill fills each pair of adjacent STI structures; and

semiconductor devices disposed on the substrate between the at least two pairs of adjacent STI structures, wherein the semiconductor devices are partitioned into groups based on function, and wherein the at least two pairs of group STI structures have different bottom depths, and

wherein the first depth and the second depth for each pair of adjacent STI structures are based on semiconductor device characteristics of the semiconductor devices.

2. The integrated circuit of claim 1, wherein the semiconductor device characteristics comprise device geometry, drive current, threshold voltage, junction voltage, and device density.

3. The integrated circuit of claim 2, wherein the semiconductor devices disposed on the substrate between a pair of STI structures share similar semiconductor device characteristics.

4. The integrated circuit of claim 1, wherein each group of semiconductor devices is disposed on the substrate between an adjacent pair of group STI structures disjoint from adjacent pairs of group STI structures of other groups of semiconductor devices.

5. The integrated circuit of claim 1, wherein the oxide fill comprises silicon dioxide.

6. An integrated circuit comprising:

a first STI structure in a substrate, the first STI structure having a first bottom depth at a first distance from a top surface of the substrate, and the first STI structure filled with a dielectric material;

a second STI structure in the substrate, the second STI structure having a second bottom depth at a second distance from the top surface of the substrate, and the second STI structure filled with the dielectric material;

a third STI structure in the substrate, the third STI structure having a third bottom depth at a third distance from the top surface of the substrate, and the third STI structure filled with the dielectric material;

a fourth STI structure in the substrate, the fourth STI having a fourth bottom depth at a fourth distance from the top surface of the substrate, and the fourth STI structure filled with the dielectric material;

a first group of semiconductor devices on the substrate between the first and second STI structures, wherein the first depth and the second depth are based on semiconductor device characteristics of the first group of semiconductor devices; and

a second group of semiconductor devices on the substrate between the third and fourth STI structures, wherein the third depth and the fourth depth are based on semiconductor device characteristics of the second group of semiconductor devices.

7. The integrated circuit of claim 6, wherein the first bottom depth and the second bottom depth are substantially equal depths.

8. The integrated circuit of claim 6, wherein the first bottom depth and the second bottom depth are different depths.

9. The integrated circuit of claim 6, wherein the first group of semiconductor devices have similar semiconductor device characteristics.

10. The integrated circuit of claim 6, wherein the first bottom depth and the second bottom depth are deeper than the third bottom depth and the fourth bottom depth, and wherein the first group of semiconductor devices are amplifiers and the second group of semiconductor devices are filters.

11. An integrated circuit comprising:

a first pair of STI structures formed to a first bottom depth at a first distance from a top of the first pair of STI structures;

a second pair of STI structures formed to a second bottom depth at a second distance from a top of the second pair of STI structures, wherein second bottom depth is different from the first bottom depth;

a third pair of STI structures formed to a third bottom depth at a third distance from a top of the third pair of STI structures, wherein third bottom depth is different from the first bottom depth and the second bottom depth;

a dielectric material filling the first and second pair of STI structures;

a first group of semiconductor devices between the first pair of STI structures, wherein the first bottom depth is based on semiconductor device characteristics of the first group of semiconductor devices; and

a second group of semiconductor devices between the second pair of STI structures, wherein the second bottom depth is based on semiconductor device characteristics of the second group of semiconductor devices.

12. The integrated circuit of claim 11 further comprising:

the dielectric material filling the third pair of STI structures; and

a third group of semiconductor devices between the third pair of STI structures, wherein the third bottom depth is based on semiconductor device characteristics of the third group of semiconductor devices.

13. The integrated circuit of claim 12, wherein the first group of semiconductor devices comprises a logic core, and wherein the second group of semiconductor devices comprises analog circuitry, and wherein the third group of semiconductor devices comprises embedded memory.

14. The integrated circuit of claim 11, wherein the semiconductor device characteristics comprise device geometry, drive current, threshold voltage, junction voltage, and device density.

15. The integrated circuit of claim 11 further comprising:

a third group of semiconductor devices between the first pair of STI structures and the second pair of STI structures, wherein a portion of the third group of semiconductor devices is on the dielectric material in the STI structures, and wherein the depth of the first bottom depth and the second bottom depth are based on the semiconductor device characteristics of the third group of semiconductor devices.