Capacitor structure and method of manufacture

• US 8,610,248 B2
• Filed: 09/21/2010
• Issued: 12/17/2013
• Est. Priority Date: 02/10/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Zhong, Huicai, Liang, Qingqing
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/993,048
• Publication Number:
  US 20110233722A1
• Time in Patent Office: 1,183 Days
• Field of Search: 257/532, 257/E29.002, 257/E21.008
• US Class Current: 257/532
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/90 having vertical extensions

Abstract

The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like.

Claims

1. A capacitor structure, comprising,

a plurality of sub-capacitors stacked on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween;

and

a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel,

wherein the plurality of sub-capacitors include a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, so that each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and

each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer,

characterized in;

that the first electrode layer and the second electrode layer are made of different conductive materials;

the second electrode layer is etched from a first side of the capacitor structure to form a first recess;

the first electrode layer is etched from a second side of the capacitor structure to form a second recess; and

the first and second recesses are filled with a dielectric material to insulate the second electrode layer from the first capacitor electrode and the first electrode layer from the second capacitor electrode, respectively.

2. The capacitor structure according to claim 1, wherein the different conductive materials have different etching rate.

3. The capacitor structure according to claim 2, wherein each of the first electrode layer and the second conductive layer is the one selected from the group consisting of a metal layer, a doped polysilicon layer and any stack thereof.

4. The capacitor structure according to claim 3, wherein the metal layer is made of one selected from a group consisting of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa_x, NiTa_x, MoN_x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi_x, Ni₃Si, Pt, Ru, Ir, Mo, HfRu, RuO_x, and any of their combinations.

5. The capacitor structure according to claim 4, wherein the first electrode layer is a polysilicon layer, and the second electrode layer is a TiN layer.

6. The capacitor structure according to claim 1, wherein the first sub-capacitors and the second sub-capacitors comprise the same dielectric material.

7. The capacitor structure according to claim 1, wherein the first sub-capacitors and the second sub-capacitors comprise different dielectric materials.

8. The capacitor structure according to claim 1, wherein

the first capacitor electrode contacts all of the first electrode layers at the first side, while being electrically isolated from all of the second electrode layers;

and

the second capacitor electrode contacts all of the second electrode layers at the second side opposite to the first side, while being electrically isolated from all of the first electrode layer.

9. The capacitor structure according to claim 1, wherein the capacitor structure is formed in a shallow trench isolation region.