Semiconductor device and semiconductor assembly with lead-free solder
First Claim
Patent Images
1. A semiconductor device, comprising:
- a semiconductor substrate;
a pad region on the semiconductor substrate;
a passivation layer over the semiconductor substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region; and
a bump structure overlying the pad region and electrically connected to the pad region via the opening;
wherein the bump structure comprises a copper layer and a SnAg layer overlying the copper layer, the SnAg layer has a melting temperature between 240°
C. and 280°
C., and the Ag content in the SnAg layer ranges from 1.2 weight percent to 1.6 weight percent.
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Abstract
A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
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Citations
19 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate; a pad region on the semiconductor substrate; a passivation layer over the semiconductor substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region; and a bump structure overlying the pad region and electrically connected to the pad region via the opening; wherein the bump structure comprises a copper layer and a SnAg layer overlying the copper layer, the SnAg layer has a melting temperature between 240°
C. and 280°
C., and the Ag content in the SnAg layer ranges from 1.2 weight percent to 1.6 weight percent. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor assembly comprising:
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a first substrate; a pad region over the first substrate; a passivation layer over the first substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region; a second substrate; and a joint structure disposed between the first substrate and the second substrate and electrically connected to the pad region via the opening; wherein the joint structure comprises a bump structure between the pad region of the first substrate and the second substrate and a solder layer between the bump structure and the second substrate; wherein the solder layer comprises silver (Ag), and the Ag content in the solder layer is less than 3.0 weight percent; and wherein at least one of the first substrate and the second substrate is a semiconductor substrate comprising a through via extending from a first surface of the semiconductor substrate through the semiconductor substrate to a second surface of the semiconductor substrate and electrically connected to the bump structure. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method of forming a semiconductor device, comprising:
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providing a semiconductor substrate; forming a pad region overlying the semiconductor substrate; forming a passivation layer over the semiconductor substrate and at least a portion of the pad region, the passivation layer having an opening defined therein to expose at least another portion of the pad region; forming a copper post over the pad region, the copper post electrically connected to the pad region via the opening; forming a lead-free solder layer over the copper post, wherein the lead-free solder layer comprises silver (Ag), the lead-free solder layer has a melting temperature between 240°
C. and 280°
C., and the Ag content in the lead-free solder layer is less than 1.6 weight percent; andreflowing the lead-free solder layer. - View Dependent Claims (17, 18, 19)
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Specification