Fabricated adhesive microstructures for making an electrical connection

• US 8,610,290 B2
• Filed: 01/12/2009
• Issued: 12/17/2013
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Lewis & Clark College, Regents of the University of California (University of California)
• Original Assignee: Lewis & Clark College, Regents of the University of California (University of California)
• Inventors: Autumn, Kellar, Fearing, Ronald S., Jones, Steven D.
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US12/352,552
• Publication Number:
  US 20090146320A1
• Time in Patent Office: 1,800 Days
• Field of Search: 438/109, 438/612, 438/119, 257/783, 257/753, 257/698, 257/E23.023, 257/E21.002, 257/E21.598
• US Class Current: 257/783
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Claims

1. A substrate comprising:

a first electrically conductive component formed on the substrate and a first plurality of electrically conductive nano-fibers electrically connected to the first electrically conductive component;

a second electrically conductive component formed on the substrate and a second plurality of electrically conductive nano-fibers electrically connected to the second electrically conductive component,

wherein the electrically conductive nano-fibers of the first and second pluralities of electrically conductive nano-fibers have first ends and opposite second ends,

wherein the electrically conductive nano-fibers of the first plurality of electrically conductive nano-fibers are formed with their first ends affixed to the first electrically conductive component, and their second ends are configured to adhere to a first electrically conductive component formed on an additional substrate, to provide an adhesive force by intermolecular forces between the second ends and the first electrically conductive component, and to establish an electrical connection with the first electrically conductive component,

wherein the electrically conductive nano-fibers of the second plurality of electrically conductive nano-fibers are formed with their first ends affixed to the second electrically conductive component, and their second ends are configured to adhere to a second electrically conductive component formed on the additional substrate, to provide an adhesive force by intermolecular forces between the second ends and the second electrically conductive component, and to establish an electrical connection with the second electrically conductive component; and

a plurality of electrically insulating nano-fibers connected to the substrate, wherein the electrically insulating nano-fibers;

are deposited in between the first and the second electrically conductive components formed on the substrate, and

are configured to adhere to the additional substrate to provide an adhesive force by intermolecular forces between the electrically insulting nano-fibers and the additional substrate.

2. The substrate of claim 1, wherein at least one of the electrically conductive nano-fibers of the first plurality of electrically conductive nano-fibers is aligned at an angle relative to the first electrically conductive component.

3. The substrate of claim 1, wherein a single electrically conductive nano-fiber of the first plurality of electrically conductive nano-fibers is capable of providing a substantially normal adhesive force of between about 20 and 8,000 nano-Newtons.

4. The substrate of claim 1, wherein a single electrically conductive nano-fiber of the first plurality of electrically conductive nano-fibers is capable of providing a substantially parallel adhesive force of between about 5.00 and 2,000 nano-Newtons.

5. The substrate of claim 1, wherein a single electrically conductive nano-fiber of the first plurality of electrically conductive nano-fibers is capable of providing an adhesive force of between about 1.00 and 200 nano-Newtons.

6. The substrate of claim 1, wherein the electrically conductive nano-fibers of first plurality of electrically conductive nano-fibers are formed on a first contact pad, and the electrically conductive nano-fibers of the second plurality of electrically conductive nano-fibers are formed on a second contact pad.

7. The substrate of claim 1, wherein the first and second electrically conductive components are part of an integrated circuit chip.

8. The substrate of claim 7 wherein the additional substrate is a package.

9. The substrate of claim 7 wherein the additional substrate is a printed circuit board.

10. The substrate of claim 7, wherein the additional substrate is another integrated circuit chip.

11. The substrate of claim 1, wherein the first and second electrically conductive components are part of a printed circuit board.

12. The substrate of claim 11 wherein the additional substrate is another printed circuit board.