System and methods for generating unclonable security keys in integrated circuits

• US 8,610,454 B2
• Filed: 01/12/2011
• Issued: 12/17/2013
• Est. Priority Date: 01/12/2010
• Status: Active Grant

• Current Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Plusquellic, James, Helinski, Ryan L., Acharyya, Dhruva J.
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US13/513,941
• Publication Number:
  US 20120319724A1
• Time in Patent Office: 1,070 Days
• Field of Search: 326/8, 326/37, 726/292
• US Class Current: 326/8
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: Y04S 40/20 Information technology specific aspects, e.g. CAD, simulation, modelling, system security
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

Claims

1. A security key generating system for an integrated circuit, comprising:

a power grid having a plurality of power points, a voltage sense wire, and a plurality of intersecting striped layers;

a voltage measuring apparatus connected to said voltage sense wire;

at least one power supply electrically connected to said plurality of power points;

a ground grid electrically connected to said power grid; and

at least one stimulus-measure circuit disposed between said at least one power supply and said ground grid to derive a physical unclonable function from at least one of said power grid and said ground grid, wherein each of said at least one stimulus-measure circuit includes at least one voltage sense transistor.

2. The system of claim 1, wherein each of said at least one stimulus-measure circuit includes a shorting inverter.

3. The system of claim 1, wherein each of said at least one stimulus-measure circuit includes at least one flip-flop.

4. The system of claim 1, wherein each of said at least one stimulus-measure circuit comprises a first flip-flop and a second flip-flop each having an output connected to a shorting inverter.

5. The system of claim 4, wherein said shorting inverter further comprises a first field-effect transistor having a source connected to said at least one power supply and a drain connected to a source of a second field-effect transistor.

6. The system of claim 5, wherein each of said at least one stimulus-measure circuit further includes a third flip-flop and a voltage sense field-effect transistor.

7. The system of claim 6, wherein the output of said second flip-flop is inputted to said third flip-flop, and an output of said third flip-flop is provided to a gate of said voltage sense field-effect transistor.

8. The system of claim 7, wherein a source of said voltage sense field-effect transistor is connected to said at least one power supply, and a drain of said voltage sense field-effect transistor is connected to said voltage sense wire.

9. The system of claim 4, wherein said shorting inverter comprises two connected field-effect transistors, said first flip-flop provides an output to a gate of one of said two connected field-effect transistors, and said second flip-flop provides an output to a gate of the other of said two connected field-effect transistors.

10. The system of claim 1, wherein each of said at least one stimulus-measure circuit includes:

a first flip-flop;

a second flip-flop connected to said first flip-flop;

a third flip-flop connected to said second flip-flop;

a shorting inverter connected to said first flip-flop;

a first voltage sense field-effect transistor connected to said second flip-flop; and

a second voltage sense field-effect transistor connected to said third flip-flop.

11. The system of claim 10, further comprising:

a second voltage sense wire connected to said at least one stimulus-measure circuit;

an operational amplifier having one input connected to said second voltage sense wire and another input connected to said other voltage sense wire; and

a key generator control connected to an output of said operational amplifier.

12. The system of claim 1, wherein each of said at least one stimulus-measure circuit includes:

a plurality of flip-flops connected in series;

a decoder connected to at least one of said plurality of flip-flops;

one or more voltage sense field-effect transistors; and

a shorting inverter connected to said plurality of flip-flops.

13. The system of claim 12, wherein said decoder is a 4 to 16 inverting decoder.

14. The system of claim 12, wherein said plurality of flip-flops comprises one flip-flop connected to said shorting inverter and at least two flip-flops connected to said decoder.

15. The system of claim 12, wherein outputs of said decoder are connected to gates of said one or more voltage sense field-effect transistors.

16. The system of claim 12, wherein said shorting inverter comprises a pair of connected field-effect transistors.

17. A method of creating a physical unclonable function circuit security key, comprising the steps of:

providing a substrate;

formulating a grid on the substrate, wherein the grid includes one or more power ports;

connecting the power grid to a power supply;

inserting one or more stimulus-measure circuits, wherein each of the one or more stimulus-measure circuits includes a shorting inverter, at least one voltage sense transistor, and at least one flip-flop; and

deriving the physical unclonable function circuit security key based on a measured stimulus and response between nodes of the grid and the one or more stimulus-measure circuits.

18. The method of claim 17, wherein the security key of said deriving step is a voltage drop security key.

19. The method of claim 17, wherein the security key of said deriving step is an equivalent resistance security key.

20. The method of claim 17, wherein the grid is a power grid.

21. The method of claim 17, wherein the grid is a ground grid.