Trimming circuit and method for driving trimming circuit
First Claim
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1. A trimming circuit comprising:
- a capacitor;
a first transistor;
a second transistor; and
a third transistor,wherein one electrode of the capacitor is electrically connected to a storage node, and the other electrode of the capacitor is electrically connected to a ground potential line,wherein a gate electrode of the first transistor is electrically connected to a write terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to a power supply potential line,wherein a gate electrode of the second transistor is electrically connected to an erase terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to a ground potential line,wherein a gate electrode of the third transistor is electrically connected to the storage node,wherein the first transistor and the second transistor each include a semiconductor material whose bandgap is 2.5 eV or more, andwherein a source electrode and a drain electrode of the third transistor are electrically connected in parallel to a resistor.
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Abstract
A highly reliable trimming circuit is provided. A rewritable trimming circuit is provided. A method for driving a highly reliable trimming circuit is provided. A method for driving a rewritable trimming circuit is provided. The trimming circuit includes a storage node connected to a source electrode or a drain electrode of a transistor whose off-state leakage current is extremely low and a transistor whose gate electrode is connected to the storage node. The trimming state of an element or a circuit connected in parallel to a source electrode and a drain electrode of the transistor whose gate electrode is connected to the storage node is controlled using the transistor whose off-state leakage current is extremely low.
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Citations
10 Claims
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1. A trimming circuit comprising:
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a capacitor; a first transistor; a second transistor; and a third transistor, wherein one electrode of the capacitor is electrically connected to a storage node, and the other electrode of the capacitor is electrically connected to a ground potential line, wherein a gate electrode of the first transistor is electrically connected to a write terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to a power supply potential line, wherein a gate electrode of the second transistor is electrically connected to an erase terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to a ground potential line, wherein a gate electrode of the third transistor is electrically connected to the storage node, wherein the first transistor and the second transistor each include a semiconductor material whose bandgap is 2.5 eV or more, and wherein a source electrode and a drain electrode of the third transistor are electrically connected in parallel to a resistor. - View Dependent Claims (2)
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3. A trimming circuit comprising:
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a capacitor; a first transistor; a second transistor; and a third transistor, wherein one electrode of the capacitor is electrically connected to a storage node, and the other electrode of the capacitor is electrically connected to a ground potential line, wherein a gate electrode of the first transistor is electrically connected to a write terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to a power supply potential line, wherein a gate electrode of the second transistor is electrically connected to an erase terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to a ground potential line, wherein a gate electrode of the third transistor is electrically connected to the storage node, wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×
10−
17 A or lower, andwherein a source electrode and a drain electrode of the third transistor are electrically connected in parallel to a resistor. - View Dependent Claims (4)
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5. A method for driving a trimming circuit, the trimming circuit comprising:
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a capacitor, a first transistor, a second transistor, and a third transistor, wherein one electrode of the capacitor is electrically connected to a storage node, and the other electrode of the capacitor is electrically connected to a ground potential line, wherein a gate electrode of the first transistor is electrically connected to a write terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to a power supply potential line, wherein a gate electrode of the second transistor is electrically connected to an erase terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to a ground potential line, wherein a gate electrode of the third transistor is electrically connected to the storage node, wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×
10−
17 A or lower, andwherein a source electrode and a drain electrode of the third transistor are electrically connected in parallel to a resistor, the method comprising; a first step of inputting a signal by which the first transistor is turned on and a signal by which the second transistor is turned off to the write terminal and the erase terminal, respectively, so that a potential of the storage node is a potential at which the third transistor is turned on; and a second step of inputting a signal by which the first transistor is turned off and a signal by which the second transistor is turned off to the write terminal and the erase terminal, respectively, so that the resistor is in a trimming state. - View Dependent Claims (6, 7)
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8. A method for driving a trimming circuit, the trimming circuit comprising:
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a capacitor, a first transistor, a second transistor, and a third transistor, wherein one electrode of the capacitor is electrically connected to a storage node, and the other electrode of the capacitor is electrically connected to a ground potential line, wherein a gate electrode of the first transistor is electrically connected to a write terminal, one of a source electrode and a drain electrode of the first transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the first transistor is electrically connected to a power supply potential line, wherein a gate electrode of the second transistor is electrically connected to an erase terminal, one of a source electrode and a drain electrode of the second transistor is electrically connected to the storage node, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to a ground potential line, wherein a gate electrode of the third transistor is electrically connected to the storage node, wherein off-state leakage current per micrometer of channel width of each of the first transistor and the second transistor is 1×
10−
17 A or lower, andwherein a source electrode and a drain electrode of the third transistor are electrically connected in parallel to a resistor, the method comprising; a first step of inputting a signal by which the first transistor is turned off and a signal by which the second transistor is turned on to the write terminal and the erase terminal, respectively, so that a potential of the storage node is a potential at which the third transistor is turned off; and a second step of inputting a signal by which the first transistor is turned off and a signal by which the second transistor is turned off to the write terminal and the erase terminal, respectively, so that the resistor is in an available state. - View Dependent Claims (9, 10)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsKaneyasu, Makoto
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Primary Examiner(s)LE, DINH THANH
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Application NumberUS13/477,747Publication NumberTime in Patent Office574 DaysField of Search327/306, 327/333, 327524-525, 327/308, 333/81.RUS Class Current327/308CPC Class CodesH01L 21/8252 the substrate being a semic...H01L 27/0605 integrated circuits made of...H01L 27/0629 in combination with diodes,...H01L 27/12 the substrate being other t...
