Memory management process and apparatus for the same

• US 8,612,664 B2
• Filed: 12/29/2009
• Issued: 12/17/2013
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Coupe, David
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US13/142,590
• Publication Number:
  US 20110307643A1
• Time in Patent Office: 1,449 Days
• Field of Search: 711/5, 711/100, 711/127, 711/154
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer (400) and a second data object consumer (410); b) arranging a address translation process for mapping the real address of an object to be stored within said banks into the address of the bank; b) receiving one object produced by said producer and dividing it into stripes of reduced size; c) storing the first stripe into said first bank; d) storing the next stripe into said second bank while the preceding stripe is read by said object consumer (410); e) storing the next stripe into said first bank again while the preceding stripe is read by said object consumer (410). f) repeating e) and c) until all stripes composing said data objects have been processed; g) arranging an interlocking mechanism for locking the writing and reading process in said banks to ensure producer has enough space to forward further data, as well as receiver has indeed data to read.

Claims

1. A memory management process for optimizing access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process comprising:

a) arranging in a local memory at least a first and a second bank of storage (A, B) for temporary object exchange between a first data object producer and a second data object consumer;

b) arranging an address translation process for mapping a real address of an object to be stored within said banks into an address of each bank;

c) receiving one object produced by said producer and dividing it into stripes of reduced size;

d) storing a first stripe into said first bank;

e) storing a next stripe into said second bank while a preceding stripe is read by said object consumer;

f) storing a further next stripe into said first bank again while the preceding stripe is read by said object consumer;

g) repeating f) and d) until all stripes composing said data objects have been processed; and

h) arranging an interlocking mechanism for locking a writing and a reading process in said banks to ensure said producer has enough space to forward further data and said receiver has data to read.

2. The memory management process according to claim 1 wherein a bus matrix structure is arranged between said producer and said consumer, and between said at least first and second bank, said bus matrix structure being arranged for performing an address translation process transparent to a central processor.

3. The memory management process according to claim 1 further comprising at least one monitoring circuit and a control unit wherein said at least one monitoring circuit is associated with at least one of said banks, said at least one monitoring circuit monitoring the address, the type of command and the identification of the producer/consumer and being capable of issuing an interrupt to said control unit independently of said central processor.

4. The memory management process according to claim 1 wherein said process is applied to a graphic process and a display engine.

5. The memory management process according to claim 1 wherein said process is used in a mobile telephone.

6. A digital processing system comprising a central processor arranged with a central memory and a set of specific units communicating with each other through said memory, said system further comprising:

a) a local memory comprising at least a first and a second bank of storage (A, B) for a temporary object exchange between a first unit, said first unit being a first data object producer and a second unit, said second unit being a second data object consumer;

b) a bus matrix structure arranged for providing access of said producer/consumer to said at least first and second banks, said bus matrix structure performing an address translation process for mapping a real address of an object to be stored within said banks into an address of the bank;

c) monitoring circuits associated with each of said first and second banks of storage for monitoring an address, a type of command and an identifier of units accessing each said associated bank, said monitoring circuits being configured to issue an interrupt to a control unit independently of said central processor; and

d) said bus matrix structure being further arranged for receiving an object produced by said producer and dividing it into stripes of reduced size and for alternatively performing a writing operation in said at least first bank while the second bank is being read, said bus matrix structure being under the control of said control unit handling said interrupts generated by said monitoring circuits.

7. The memory management process according to claim 6 wherein said system is applied to a graphic process and a display engine.

8. The memory management process according to claim 6 wherein said system is used in a mobile telephone.