Memory switching control apparatus using open serial interface, operating method thereof, and data storage device therefor
First Claim
1. A memory switching control apparatus using an open serial interfacing, comprising:
- one or more processor interfacing units which perform interfacing with one or more processing units, the processing units including internal and external processing units;
one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme;
one or more of arbitrating units, which are respectively provided corresponding to the one or more memory interfacing units, to independently arbitrate usage rights of the one or more processor interfacing units to the one or more memory interfacing units; and
a memory port table which manages memory start addresses respectively allocated to the one or more memory interfacing units, memory sizes of the data storage devices connected to the memory interfacing ports or memory end addresses allocated to system addressing regions allocated to the one or more memory interfacing units, and state information of the one or more memory interfacing units,wherein each of the one or more processor interfacing units comprises;
a data buffer which temporarily stores data, a memory address, a control signal, and a state signal inputted to and outputted from the processing unit and adjusts data width and speed of data inputted to and outputted from one of the one or more memory interfacing units, anda decoder and a controller which identifies one of the one or more memory interfacing units which is to be requested to be accessed, based on the memory address, the control signal, and the state signal stored in the data buffer and the memory port table, requests for a usage right, and adjusts a data exchange timing for the one of the one or more memory interfacing units.
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Accused Products
Abstract
Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.
26 Citations
23 Claims
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1. A memory switching control apparatus using an open serial interfacing, comprising:
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one or more processor interfacing units which perform interfacing with one or more processing units, the processing units including internal and external processing units; one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; one or more of arbitrating units, which are respectively provided corresponding to the one or more memory interfacing units, to independently arbitrate usage rights of the one or more processor interfacing units to the one or more memory interfacing units; and a memory port table which manages memory start addresses respectively allocated to the one or more memory interfacing units, memory sizes of the data storage devices connected to the memory interfacing ports or memory end addresses allocated to system addressing regions allocated to the one or more memory interfacing units, and state information of the one or more memory interfacing units, wherein each of the one or more processor interfacing units comprises; a data buffer which temporarily stores data, a memory address, a control signal, and a state signal inputted to and outputted from the processing unit and adjusts data width and speed of data inputted to and outputted from one of the one or more memory interfacing units, and a decoder and a controller which identifies one of the one or more memory interfacing units which is to be requested to be accessed, based on the memory address, the control signal, and the state signal stored in the data buffer and the memory port table, requests for a usage right, and adjusts a data exchange timing for the one of the one or more memory interfacing units. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9)
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6. The memory switching control apparatus of 5, wherein the ID is generated by combining information of a processor interfacing unit which issues the memory-accessing request and specific request sequence information of the processor interfacing unit, wherein the processor interfacing unit is one of the one or more processor interfacing units.
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10. A memory switching control apparatus using an open serial interfacing, comprising:
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one or more processor interfacing units which perform interfacing with one or more processing units, the processing units including internal and external processing units; one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; one or more of arbitrating units, which are respectively provided corresponding to the one or more memory interfacing units, to independently arbitrate usage rights of the one or more processor interfacing units to the one or more memory interfacing units; and a memory port table which manages memory start addresses respectively allocated to the one or more memory interfacing units, memory sizes of the data storage devices connected to the memory interfacing ports or memory end addresses allocated to system addressing regions allocated to the one or more memory interfacing units, and state information of the one or more memory interfacing units, wherein each of the one or more memory interfacing units comprises; a link unit which generates memory packets by combining data bus signals and control bus signals applied by the one or more processor interfacing units, converts the memory packets to interfacing line packets by adjusting data widths of the memory packets, converts the interfacing line packets to memory packets, and extracts data bus signals and control bus signals from the memory packets, and a physical-layer processor which performs a physical-layer process on the interfacing line packets inputted and outputted between the link unit and interfacing lines, wherein the link unit comprises; a data input/output bus through which data bus signals including reading data and writing data are inputted to and outputted from the one or more processor interfacing units, a control input bus through which control bus signals including memory addresses, reading control signals, writing control signals, and state signals are inputted from the one or more processor interfacing units, a control output bus through which the control bus signals including the memory addresses, the reading control signals, the writing control signals, and the state signals are outputted to the one or more processor interfacing units, a data mixing/extracting unit which mixes the data bus signals inputted through the data input/output bus and the control bus signals inputted through the control input bus to output memory packets and extracts data bus signals and control bus signals from inputted memory packets to output the data bus signals and the control bus signals through the data input/output bus and the control output bus, and an asymmetric buffer unit which adjusts widths of the memory packets outputted from the data mixing/extracting unit to convert the memory packets to interfacing line packets or adjusts data widths of the inputted interfacing line packets to convert the interfacing line packets to the memory packets to output the memory packets to the data mixing/extracting unit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An operating method of a memory switching control apparatus using an open serial interfacing scheme, the memory switching control apparatus having a plurality of processor interfacing units connected to a plurality of processing units, a plurality of memory interfacing units connected to a plurality of data storage devices, and a plurality of arbitrating units arbitrating usage right to the plurality of memory interfacing units, the operating method comprising:
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if an initialization operation is started, driving the plurality of memory interfacing units at corresponding lowest speeds so as to check the number of available interfacing lines; checking a highest speed of the checked available interfacing lines; and driving all the checked available interfacing lines at the checked highest speed so as to determine whether or not the available interfacing lines operate normally; measuring data delays between the interfacing lines that are determined to operate normally and compensating for the data delays between the interfacing lines; performing a memory test for data storage devices connected to the normally-operated interfacing lines; and if the result of the memory test is normal, allocating system addressing spaces mapped to the data storage devices to each of the plurality of memory interfacing units and registering thereof in a memory port table. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A data storage device comprising:
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one or more memory devices; and one or more memory interfacing units, each of which an open-serial-interfacing scheme memory interfacing port separately or commonly connected to the memory devices, wherein each of the one or more memory interfacing units comprises; a link unit which generates memory packets by combining data bus signals and control bus signals applied by one or more processor interfacing units, converts the memory packets to interfacing line packets by adjusting data widths of the memory packets, converts the interfacing line packets to memory packets, and extracts data bus signals and control bus signals from the memory packets, and a physical-layer processor which performs a physical-layer process on the interfacing line packets inputted and outputted between the link unit and interfacing lines, wherein the link unit comprises; a data input/output bus through which data bus signals including reading data and writing data are inputted to and outputted from the one or more processor interfacing units, a control input bus through which control bus signals including memory addresses, reading control signals, writing control signals, and state signals are inputted from the one or more processor interfacing units, a control output bus through which the control bus signals including the memory addresses, the reading control signals, the writing control signals, and the state signals are outputted to the one or more processor interfacing units, a data mixing/extracting unit which mixes the data bus signals inputted through the data input/output bus and the control bus signals inputted through the control input bus to output memory packets and extracts data bus signals and control bus signals from inputted memory packets to output the data bus signals and the control bus signals through the data input/output bus and the control output bus, and an asymmetric buffer unit which adjusts widths of the memory packets outputted from the data mixing/extracting unit to convert the memory packets to interfacing line packets or adjusts data widths of the inputted interfacing line packets to convert the interfacing line packets to the memory packets to output the memory packets to the data mixing/extracting unit.
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Specification